ZHCSGS2A September 2017 – September 2017 TS5USBC402
PRODUCTION DATA.
| PARAMETER | TEST CONDITIONS | MIN | TYP | MAX | UNIT | |||
|---|---|---|---|---|---|---|---|---|
| SUPPLY | ||||||||
| VCC | Power supply voltage | 2.3 | 5.5 | V | ||||
| ICC | Active supply current | OE = 0 V SEL1, SEL2 = 0 V, 1.8 V or VCC 0 V < VI/O < 3.6 V |
72 | 100 | µA | |||
| Supply current during OVP condition | OE = 0 V SEL1, SEL2 = 0 V, 1.8 V or VCC VI/O > VPOS_THLD |
80 | 120 | µA | ||||
| ICC_PD | Standby powered down supply current | OE = 1.8 V or VCC SEL1 = 0 V, 1.8 V, or VCC SEL2 = 0 V, 1.8 V, or VCC |
2.2 | 10 | µA | |||
| DC Characteristics | ||||||||
| RON | ON-state resistance | VI/O = 0.4 V ISINK = 8 mA Refer to ON-State Resistance Figure |
5.6 | 9 | Ω | |||
| ΔRON | ON-state resistance match between channels | VI/O = 0.4 V ISINK = 8 mA Refer to ON-State Resistance Figure |
0.07 | 0.3 | Ω | |||
| RON (FLAT) | ON-state resistance flatness | VI/O = 0 V to 0.4 V ISINK = 8 mA Refer to ON-State Resistance Figure |
0.07 | 0.4 | Ω | |||
| IOFF | I/O pin OFF leakage current | VD± = 0 V or 3.6 V VCC = 2.3 V to 5.5 V VD1±or VD2+/- = 3.6 V or 0 V Refer to Off Leakage Figure |
-1 | 1.2 | 6 | µA | ||
| VD± = 0 V or 20 V VCC = 2.3 V to 5.5 V VD1± or VD2+/- = 0 V Refer to Off Leakage Figure |
-1 | 165 | 200 | µA | ||||
| ION | ON leakage current | VD± = 0 V or 3.6 V VD1± and VD2+/- = high-Z Refer to On Leakage Figure |
-1 | 1.2 | 6 | µA | ||
| Digital Characteristics | ||||||||
| VIH | Input logic high | SEL1, SEL2, OE | 1.4 | V | ||||
| VIL | Input logic low | SEL1, SEL2, OE | 0.5 | V | ||||
| VOL | Output logic low | FLT IOL = 3 mA |
0.4 | V | ||||
| IIH | Input high leakage current | SEL1, SEL2, OE = 1.8 V, VCC | -1 | 1 | 5 | μA | ||
| IIL | Input low leakage current | SEL1, SEL2, OE = 0 V | -1 | ±0.2 | 5 | μA | ||
| RPD | Internal pull-down resistor on digital input pins | 6 | MΩ | |||||
| CI | Digital input capacitance | SEL1, SEL2 = 0 V, 1.8 V or VCC f = 1 MHz |
3.4 | pF | ||||
| Protection | ||||||||
| VOVP_TH | OVP positive threshold | 4.5 | 4.8 | 5.2 | V | |||
| VOVP_HYST | OVP threshold hysteresis | 75 | 230 | 425 | mV | |||
| VCLAMP_V | Maximum voltage to appear on D1± and D2± pins during OVP scenario | VD± = 0 to 18 V tRISE and tFALL(10% to 90 %) = 100 ns RL = Open Switch on or off OE = 0 V |
0 | 9.6 | V | |||
| VD± = 0 to 18 V tRISE and tFALL(10% to 90 %) = 100 ns RL = 50Ω Switch on or off OE = 0 V |
0 | 9.0 | V | |||||
| tEN_OVP | OVP enable time | RPU = 10 kΩ to VCC (FLT) CL = 35 pF Refer to OVP Timing Diagram Figure |
0.6 | 3 | μs | |||
| tREC_OVP | OVP recovery time | RPU = 10 kΩ to VCC (FLT) CL = 35 pF Refer to OVP Timing Diagram Figure |
1.5 | 5 | μs | |||