8.2.2.1.1 Power-On Reset

Based on design principles and extensive tests with TSC2013-Q1 device, the power of the device must meet a specific on-off timing and sequence to ensure the POR is implemented during each TSC2013-Q1 power on. This specific timing and sequence also ensures that a lockup is prevented.

During the device power on, the POR brings the TSC2013-Q1 device into a known default working state by initializing the internal state machine, data and control registers, and the condition of the output pins. Without the POR, the TSC2013-Q1 device can power on in a random state and can cause the PINTDAV pin to respond incorrectly.

The TSC2013-Q1 POR circuit was designed to not consume power during normal operation. The power-down current is kept as low as possible (0.8-µA maximum power-down supply current).

This POR circuit in TSC2013-Q1 device requires specific power-up and power-down ramps and sequences.

Figure 48 shows and Table 17 lists the recommended power-off times, on-ramp, and off-ramp specifications.

Figure 48. POR Sequence

8.2.2.1.2 Requesting a Minimal t_{(SNSVDD_OFF)} Time

The POR circuit of the TSC2013-Q1 device contains a capacitor that is charged when the device powers up which generates an internal reset signal. This capacitor is discharged after the TSC2013-Q1 supply is switched off. The TSC2013-Q1 device is designed for low-power operation, therefore the POR requires time to charge and discharge the capacitor, especially under cold temperatures (less than –20°C). If the SNSVDD off time is not sufficient, the device can lock up. Only a power recycle can resolve this lockup condition.

8.2.2.1.3 Requesting a Minimal t_{(SNSVDD_OFF_ramp)} and t_{(SNSVDD_ON_ramp)} Ramp

To ensure proper initialization of the TSC2013-Q1 device, the device must reach a certain voltage before the internal POR signal is released. If the power supply on the ramp is too slow the device can power up in a random state which can cause a lock up.

The capacitor inside the POR circuit must be discharged through the SNSVDD pin. To support a proper discharge when the TSC2013-Q1 supply is switched off, TI recommends to provide a low resistance path on the SNSVDD pin.

8.2.2.1.4 Hardware Reset

The hardware reset pin, RESET, is available to perform a system reset which resets the device if the pulse width meets the timing requirement (at least 10-µs wide and the SNSVDD/VREF or I/OVDD pin is greater than or equal to 1.6 V). Any reset pulse less than 5 µs is rejected. To accommodate the timing drift between devices because of process variation, a reset pulse width between 5 µs and 10 µs is not recognized and the result is undetermined. This situation should be avoided. A good reset pulse must be low for at least 10 µs (SNSVDD/VREF or I/OVDD pin is greater than or equal to 1.6 V). An internal spike filter rejects spikes up to 20 ns wide. See Figure 37 for the hardware reset timing diagram.

8.2.2.1.5 Software Reset

During normal operation a software reset can be sent by the host processor to the device by setting the SWRST bit (D1) to 1 in the control byte 1 (see Table 6).

8.2.2.2.1 Power-Off Cycles During Normal Operation

The TSC2013-Q1 device is a low-power device and therefore switching the TSC2013-Q1 device off during normal operation is not needed nor recommended.

Every power cycle (power on → power off → power on) must meet the requirements described in the Power-On Reset section. If requirements cannot be met, TI recommends to issue a hardware reset after every power cycle.

8.2.2.2.2 Supply Glitches During Normal Operation

A TSC2013-Q1 SNSVDD or IOVDD power glitch during normal operation can cause a lockup condition. Therefore ensure that the system is able to either recycle the power in the system following the requirements described in the Power-On Reset section or issue a hardware reset as described in the Hardware Reset section.

8.2.2.2.3 TSC2013-Q1 Digital Pins

In many applications, users use the same power supply for both the TSC2013-Q1 analog and digital supplies. The SNSVDD supply is connected with the I/OVDD supply. Under such cases, the logic high status on the TSC2013-Q1 digital pins before power-up become a concern when performing a proper POR.

Table 18 lists the digital I/O pins of the TSC2013-Q1 device.

Every TSC2013-Q1 pin is well protected against ESD strikes. The TSC2013-Q1RESET, A0, and A1 pins have the same protection as the SDA and SCL pins. This protection allows the RESET, A0, and A1 pins to be pulled high before the device powers on without activating an internal ESD diode and without causing a power up of the TSC2013-Q1.

The output pin, PINTDAV, is a digital output pin. The host processor must define the PINTDAV pin as an input to the host processor without any pullup-pulldown feature. In some cases the default of the host processor is an output with an enabled pullup-pulldown feature but the host-processor firmware changes this definition at a later point to an input. If the TSC2013-Q1 device is not powered up, a power up can also occur through the ESD cells as shown in by the red line in Figure 49. This power up is considered a false power up. A false power up cannot ensure a proper power supply to the device or a proper POR.

In case the TSC2013-Q1 device is powered up, both the device and drive processor drive different levels on the same line resulting in high power consumption.

The TSC2013-Q1PINTDAV pin should be connected to the correct pin on the host processor to avoid bus conflicts and illegal powering up of the TSC2013-Q1 device.

Figure 49. Internal ESD Protection Diodes at the TSC2013-Q1PINTDAV Pin

8.2.2.2.4 Suggested Hardware Reset During Power-On

The suggested sequence during power up is the following:

• Keep RESET pin low
• Wait for the supplies to settle
• Wait for at least 10µs before releasing the RESET pin

Figure 50 shows the suggested waveform.

Figure 50. Suggested RESET Waveform During Power-On

8.2.2.3.1 Touch-Panel Driving Power

On a resistive touch-screen system, the driving current of the touch panel, provided by the TSC device through the analog interface, has the highest impact on the power consumption in the touch screen system. This touch-panel power consumption is decided by the resistance of the touch panel and the TSC power-supply (SNSVDD) voltage. Figure 51 shows this relationship. The touch screen is driven by the TSC from the SNSVDD supply and the resistance of the panel determines the peak drive current.

Figure 51 only shows the ideal TSC driving condition where the internal resistance of the TSC is ignored because the resistance is small (5 to 6 Ω) compared to the resistance of the touch panel (100s to 1000s Ω). Therefore the actual power consumption should be a little less than that shown in Figure 51.

A user can reduce power consumption in three ways:

• Using touch screens with higher resistance
• Using a low-power supply, SNSVDD, to the TSC
• Reducing the driver on-time or the on-off ratio of the driver

Touch panels with higher resistance are likely to cause more noise and longer settling time which limits the options for users.

The TSC20013-Q1 device is designed with a power supply, SNSVDD, range of 1.6 V to 3.6 V.

Reducing the driver on-time involves setting various touch-screen timings and delays. lists the relevant parameters concerning these timings and delays. The following sections describe the functions and effects of these timings and delays. See the Register Maps section for the timing settings of the configuration registers.

8.2.2.3.2 ADC Clock Effects

A TSC2013-Q1 device contains a nominal 4-MHz internal clock that is used to drive the state machines inside the device which performs the many functions. This clock is divided down to provide a clock to run the SAR ADC (analog-to-digital converter). If the 4-MHz clock is used directly (divided by 1), the ADC is limited to a 10-bit resolution, then using higher resolutions at this speed does not result in accurate conversions. The 12-bit resolution requires that the conversion clock run at either 2 MHz (divided by 2) or 1 MHz (divided by 4). The division ratio for the ADC clock is set in the configuration register 0 (CFR0), by setting the CL1 and CL0 bits (see Table 6).

The ability to change the conversion clock rate allows the user to select the optimal value for the ADC resolution, speed, and power dissipation. Higher clock frequency results in faster touch-data converting speed and shorter touch-driver on-time which usually result in lower SNSVDD power consumption. Figure 52 and Figure 53 show examples of the ADC clock effect on the analog interface traffic (X+, X–, Y+, and Y– lines). In these figures, a TSC drives the touch panel to acquire the X, Y, Z1, and Z2 coordinates and three samples-per-coordinate. Figure 52 shows an analog interface with the clock frequency set to 2 MHz. Figure 53 shows an analog interface with the clock frequency set to 1-MHz. In Figure 52 and Figure 53, other than the ADC clock frequency difference, all other settings are completely identical with the following values: PVS equal to 0 µs, PR equal to 20 µs, and SN equal to 32 µs (see the Panel Voltage Stabilization Time section for more information on these timers).

The ADC clock frequency determines the length of the TSC acquisition time and TSC driver on-time. The faster the ADC clock, the shorter the driver on-time. For example, sampling 3 Y data with an ADC clock value of 2 MHz (see Figure 52) uses only about half of the time compared to sampling the data with an ADC clock value of 1 MHz (see Figure 53).

Use Equation 10 to calculate the analog power-supply current, I_(SNSVDD).

Equation 10.

where

• f(V_(SNSVDD)) is a function of V_(SNSVDD)
• V_(SNSVDD) is the SNSVDD voltage (in V)
• R is the average resistance of the touch panel (in Ω)
• SSPS is sample sets-per-second, which indicates how many sets of touch data is received by the host within a second
• S is the number of data in a set of samples
• B is the TSC resolution, either 10 bit or 12 bit
• ƒ_(OSC) is ADC clock frequency, which can be 4, 2, or 1 MHz

Equation 10 includes two parts: the internal circuitry power consumption or f(V_(SNSVDD)) and the current to drive the external resistive-touch panel which is calculated using Equation 11.

Equation 11.

A concern for using the faster ADC clock is because of the settling time or transients of the analog interface. The higher clock frequency can reduce the accuracy of the data in those cases where the TSC begins the data acquisitions before the analog interface lines reach the stable voltages. Therefore, adding some delays on the analog interface in order to wait for the interface to become stable before an ADC begins working might be necessary. These delays can include the panel voltage-stabilization time, the precharge time of the pins, the sense time (see the Panel Voltage Stabilization Time section), or a combination.