ZHCSHW9C March 2018 – July 2024 TUSB1002A
PRODUCTION DATA
请参考 PDF 数据表获取器件具体的封装图。
The TUSB1002A has (MODE, CFG1, CFG2, CH1_EQ1, CH1_EQ2, CH2_EQ1, and CH2_EQ2) 4-level inputs pins that are used to control the equalization gain and the output voltage swing dynamic range. These 4-level inputs use a resistor divider to help set the four valid levels and provide a wider range of control settings. These resistors together with the external resistor connection combine to achieve the desired voltage level.
| LEVEL | SETTINGS |
|---|---|
| 0 | Option 1: Tie 1kΩ 5% to GND. Option 2: Tie directly to GND. |
| R | Tie 20kΩ 5% to GND. |
| F | Float (leave pin open) |
| 1 | Option 1: Tie 1kΩ 5% to VCC. Option 2: Tie directly to VCC. |
To conserve power, the TUSB1002A disables 4-level input’s internal pullup/pulldown resistors after the state of 4-level pins have been sampled on rising edge of EN. A change of state for any four level input pin is not applied to TUSB1002A until after EN pin transitions from low to high.