ZHCSHW9C March   2018  – July 2024 TUSB1002A

PRODUCTION DATA  

  1.   1
  2. 1 特性
  3. 2 应用
  4. 3 说明
  5. 4 Pin Configuration and Functions
  6. 5 Specifications
    1. 5.1 Absolute Maximum Ratings
    2. 5.2 ESD Ratings
    3. 5.3 Recommended Operating Conditions
    4. 5.4 Thermal Information
    5. 5.5 Electrical Characteristics
    6. 5.6 Timing Requirements
    7. 5.7 Switching Characteristics
    8. 5.8 Typical Characteristics
  7. 6 Detailed Description
    1. 6.1 Overview
    2. 6.2 Functional Block Diagram
    3. 6.3 Feature Description
      1. 6.3.1 4-Level Control Inputs
      2. 6.3.2 Linear Equalization
      3. 6.3.3 Adjustable VOD Linear Range and DC Gain
      4. 6.3.4 USB3.2 Dual Channel Operation (MODE = “F”)
      5. 6.3.5 USB3.2 Single Channel Operation (MODE = “1”)
      6. 6.3.6 PCIe/SATA/SATA Express Redriver Operation (MODE = “R”; CFG1 = "0"; CFG2 = "0" )
      7. 6.3.7 Basic Redriver Operation (MODE = “0”)
    4. 6.4 Device Functional Modes
      1. 6.4.1 Shutdown Mode
      2. 6.4.2 Disconnect Mode
    5. 6.5 U0 Mode
    6. 6.6 U1 Mode
    7. 6.7 U2/U3 Mode
  8. 7 Application and Implementation
    1. 7.1 Application Information
    2. 7.2 Typical USB3.2 Application
      1. 7.2.1 Design Requirements
      2. 7.2.2 Detailed Design Procedure
      3. 7.2.3 ESD Protection
      4. 7.2.4 Application Curves
    3. 7.3 Typical SATA, PCIe and SATA Express Application
      1. 7.3.1 Design Requirements
      2. 7.3.2 Detailed Design Procedure
      3. 7.3.3 Application Curves
    4. 7.4 Power Supply Recommendations
    5. 7.5 Layout
      1. 7.5.1 Layout Guidelines
      2. 7.5.2 Layout Example
  9. 8 Device and Documentation Support
    1. 8.1 接收文档更新通知
    2. 8.2 支持资源
    3. 8.3 Trademarks
    4. 8.4 静电放电警告
    5. 8.5 术语表
  10. 9 Revision History
  11. 10Mechanical, Packaging, and Orderable Information

封装选项

请参考 PDF 数据表获取器件具体的封装图。

机械数据 (封装 | 引脚)
  • RGE|24
散热焊盘机械数据 (封装 | 引脚)
订购信息

4 Pin Configuration and Functions

TUSB1002A RGE Package, 24-Pin VQFN (Top View)Figure 4-1 RGE Package, 24-Pin VQFN (Top View)
Table 4-1 Pin Functions
PIN TYPE INTERNAL PULLUP PULLDOWN DESCRIPTION
NAME NO.
RX1P 9 90Ω Differential Input — Differential input for SuperSpeed (SS) and SuperSpeedPlus (SSP) positive signals for Channel 1
RX1N 8 Differential input for SuperSpeed (SS) and SuperSpeedPlus (SSP) negative signals for Channel 1
RX2P 19 90Ω Differential Input — Differential input for SuperSpeed (SS) and SuperSpeedPlus (SSP) positive signals for Channel 2
RX2N 20 Differential input for SuperSpeed (SS) and SuperSpeedPlus (SSP) negative signals for Channel 2.
TX1P 22 90Ω Differential Output — Differential output for SuperSpeed (SS) and SuperSpeedPlus (SSP) positive signals for Channel 1.
TX1N 23 Differential output for SuperSpeed (SS) and SuperSpeedPlus (SSP) negative signals for Channel 1.
TX2P 12 90Ω Differential Output — Differential output for SuperSpeed (SS) and SuperSpeedPlus (SSP) positive signals for Channel 2.
TX2N 11 Differential output for SuperSpeed (SS) and SuperSpeedPlus (SSP) negative signals for Channel 2.
CH1_EQ1 2 I (4-level) PU (approx 45K)
PD (approx 95K)		 CH1_EQ1. Configuration pin used to control Rx EQ level for RX1P/N. The state of this pin is sampled after the rising edge of EN. Refer to Figure 5-2 for details of timing. This pin along with CH1_EQ2 allows for up to 16 equalization settings.
CH1_EQ2 3 I (4-level) CH1_EQ2. Configuration pin used to control Rx EQ level for RX1P/N. The state of this pin is sampled after the rising edge of EN. Refer to Figure 5-2 for details of timing. This pin along with CH1_EQ1 allows for up to 16 equalization settings.
CH2_EQ1 16 I (4-level) CH2_EQ1. Configuration pin used to control Rx EQ level for RX2P/N. The state of this pin is sampled after the rising edge of EN. Refer to Figure 5-2 for details of timing. This pin along with CH2_EQ2 allows for up to 16 equalization settings.
CH2_EQ2 17 I (4-level) CH2_EQ2. Configuration pin used to control Rx EQ level for RX2P/N. The state of this pin is sampled after the rising edge of EN. Refer to Figure 5-2 for details of timing. This pin along with CH2_EQ1 allows for up to 16 equalization settings.
EN 5 I (2-level) PU (approx 400 K) EN. Places TUSB1002A into shutdown mode when asserted low. Normal operation when pin is asserted high. When in shutdown, TUSB1002A’s receiver terminations are high impedance and tx/rx channels are disabled.
CFG1 4 I (4-level) PU (approx 45K)
PD (approx 95K)		 CFG1. This pin along with CFG2 selects the VOD linearity range and DC gain for both channels 1 and 2. The state of this pin is sampled after the rising edge of EN. Refer to Figure 5-2 for details of timing. Refer to Table 6-3 for VOD linearity range and DC gain options.
CFG2 15 I (4-level) PU (approx 45K)
PD (approx 95K)		 CFG2. This pin along with CFG1 sets the VOD linearity range and DC gain for both channels 1 and 2. The state of this pin is sampled after the rising edge of EN. Refer to Figure 5-2 for details of timing. Refer to Table 6-3 for VOD linearity range and DC gain options.
MODE 7 I (4-level) PU (approx 45 K)
PD (approx 95K)		 MODE. This pin is for selecting different modes of operation. The state of this pin is sampled after the rising edge of EN. Refer to Figure 5-2 for details of timing.
0 = Basic Redriver Mode.
R = PCIe / Test Mode. PCIe Mode and TI Internal use only
F = USB3.2 x1 Dual Channel Operation enabled (TUSB1002A normal mode).
1 = USB3.2 x1 Single-channel operation.
RSVD1 24 O — RSVD1. Under normal operation, this pin is driven low by TUSB1002A. Recommend leaving this pin unconnected on PCB.
DCBOOST# 14 I (2-level) PU (approx 400 K) DCBOOST#. This pin when asserted low increases the DC Gain level defined inTable 6-3 by +1dB unless already at +2dB. If DC Gain level defined inTable 6-3 is already at +2dB, then asserting this pin low will not change the DC Gain level. This pin can be left unconnected if this function is not needed.
1 = DC Gain defined by Table 6-3.
0 = DC Gain defined by Table 6-3 is increased by +1dB.
VCC 1, 13 Power — 3.3V (±10%) Supply.
GND 6, 10, 18, 21 GND — Ground
Thermal pad — Thermal pad. Recommend connecting to a solid ground plane.
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