米6体育平台手机版

ZHCSHW9C March 2018 – July 2024 TUSB1002A

PRODUCTION DATA

请参考 PDF 数据表获取器件具体的封装图。

5.6 Timing Requirements

over operating free-air temperature and voltage range (unless otherwise noted)

		MIN	MAX	UNIT
t_{d_pg}	Internal power good asserted high when V_CC is at 2.5V		5	µs
t_{CFG_SU}	CFG⁽¹⁾ pins setup before internal Reset⁽²⁾ high	0		µs
t_{CFG_HD}	CFG⁽¹⁾ pins hold after internal Reset⁽²⁾ high	500		µs
t_{VCC_RAMP}	V_CC supply ramp requirement	0.1	50	ms

(1) Following pins comprise CFG pins: MODE, CFG[2:1], CH1_EQ[2:1], CH2_EQ[2:1]

(2) Internal reset is the logical AND of EN pin and internal power good.