ZHCSHW9C March 2018 – July 2024 TUSB1002A
PRODUCTION DATA
- 1
- 1 特性
- 2 应用
- 3 说明
- 4 Pin Configuration and Functions
- 5 Specifications
-
6 Detailed Description
- 6.1 Overview
- 6.2 Functional Block Diagram
- 6.3
Feature Description
- 6.3.1 4-Level Control Inputs
- 6.3.2 Linear Equalization
- 6.3.3 Adjustable VOD Linear Range and DC Gain
- 6.3.4 USB3.2 Dual Channel Operation (MODE = “F”)
- 6.3.5 USB3.2 Single Channel Operation (MODE = “1”)
- 6.3.6 PCIe/SATA/SATA Express Redriver Operation (MODE = “R”; CFG1 = "0"; CFG2 = "0" )
- 6.3.7 Basic Redriver Operation (MODE = “0”)
- 6.4 Device Functional Modes
- 6.5 U0 Mode
- 6.6 U1 Mode
- 6.7 U2/U3 Mode
- 7 Application and Implementation
- 8 Device and Documentation Support
- 9 Revision History
- 10Mechanical, Packaging, and Orderable Information
封装选项
请参考 PDF 数据表获取器件具体的封装图。
机械数据 (封装 | 引脚)
- RGE|24
散热焊盘机械数据 (封装 | 引脚)
- RGE|24
订购信息
6.3.2 Linear Equalization
With a linear equalizer, the TUSB1002A can electrically shorten a particular channel allowing for longer run lengths.
Figure 6-1 Linear EqualizerWith a TUSB1002A, a longer trace can be made to have similar insertion loss as a shorter trace. For example, a long trace of X + Y inches can be made to have similar loss characteristics of a shorter trace of X inches.
The receiver equalization level for each channel is determined by the state of the CHx_EQ1 and CHx_EQ2 pins, where x = 1 or 2.
Table 6-2 EQ Configuration Options for 1200mV Linearity 0dB DC Gain Setting
| EQ SETTING # | CHx_EQ2 PIN LEVEL | CHx_EQ1 PIN LEVEL | EQ GAIN at 2.5GHz / 5GHz (dB) |
|---|---|---|---|
| 1 | 0 | 0 | 1.0 / 3.6 |
| 2 | 0 | R | 2.1 / 5.5 |
| 3 | 0 | F | 3.0 / 6.8 |
| 4 | 0 | 1 | 4.0 / 8.1 |
| 5 | R | 0 | 4.6 / 9.0 |
| 6 | R | R | 5.5 / 10.0 |
| 7 | R | F | 6.2 / 10.8 |
| 8 | R | 1 | 6.9 / 11.6 |
| 9 | F | 0 | 7.3 / 11.9 |
| 10 | F | R | 7.9 / 12.6 |
| 11 | F | F | 8.4 / 13.1 |
| 12 | F | 1 | 9.0 / 13.7 |
| 13 | 1 | 0 | 9.4 / 14.1 |
| 14 | 1 | R | 9.9 / 14.6 |
| 15 | 1 | F | 10.3 / 14.9 |
| 16 | 1 | 1 | 10.7 / 15.3 |