Figure 6-2 I2C Write with Data

The following procedure should be followed to write data to TUSB1004 I²C registers (refer to Figure 6-2):

1. The controller initiates a write operation by generating a start condition (S), followed by the TUSB1004 7-bit address and a zero-value “W/R” bit to indicate a write cycle.
2. The TUSB1004 acknowledges the address cycle.
3. The controller presents the register offset within TUSB1004 to be written, consisting of one byte of data, MSB-first.
4. The TUSB1004 acknowledges the sub-address cycle.
5. The controller presents the first byte of data to be written to the I²C register.
6. The TUSB1004 acknowledges the byte transfer.
7. The controller may continue presenting additional bytes of data to be written, with each byte transfer completing with an acknowledge from the TUSB1004.
8. The controller terminates the write operation by generating a stop condition (P).

Figure 6-3 I2C Read Without Repeated Start

The following procedure should be followed to read the TUSB1004 I²C registers without a repeated Start (refer Figure 6-3).

1. The controller initiates a read operation by generating a start condition (S), followed by the TUSB1004 7-bit address and a zero-value “W/R” bit to indicate a read cycle.
2. The TUSB1004 acknowledges the 7-bit address cycle.
3. Following the acknowledge the controller continues sending clock.
4. The TUSB1004 transmit the contents of the memory registers MSB-first starting at register 00h or last read register offset+1. If a write to the I²C register occurred prior to the read, then the TUSB1004 shall start at the register offset specified in the write.
5. The TUSB1004 waits for either an acknowledge (ACK) or a not-acknowledge (NACK) from the controller after each byte transfer; the I²C controller acknowledges reception of each data byte transfer.
6. If an ACK is received, the TUSB1004 transmits the next byte of data as long as controller provides the clock. If a NAK is received, the TUSB1004 stops providing data and waits for a stop condition (P).
7. The controller terminates the write operation by generating a stop condition (P).

Figure 6-4 I2C Read with Repeated Start

The following procedure should be followed to read the TUSB1004 I²C registers with a repeated Start (refer Figure 6-4).

1. The controller initiates a read operation by generating a start condition (S), followed by the TUSB1004 7-bit address and a zero-value “W/R” bit to indicate a write cycle.
2. The TUSB1004 acknowledges the 7-bit address cycle.
3. The controller presents the register offset within TUSB1004 to be written, consisting of one byte of data, MSB-first.
4. The TUSB1004 acknowledges the register offset cycle.
5. The controller presents a repeated start condition (Sr).
6. The controller initiates a read operation by generating a start condition (S), followed by the TUSB1004 7-bit address and a one-value “W/R” bit to indicate a read cycle.
7. The TUSB1004 acknowledges the 7-bit address cycle.
8. The TUSB1004 transmit the contents of the memory registers MSB-first starting at the register offset.
9. The TUSB1004 shall wait for either an acknowledge (ACK) or a not-acknowledge (NACK) from the controller after each byte transfer; the I²C controller acknowledges reception of each data byte transfer.
10. If an ACK is received, the TUSB1004 transmits the next byte of data as long as controller provides the clock. If a NAK is received, the TUSB1004 stops providing data and waits for a stop condition (P).
11. The controller terminates the read operation by generating a stop condition (P).

Figure 6-5 I2C Write Without Data

The following procedure should be followed for setting a starting sub-address for I²C reads (refer to Figure 6-5).

1. The controller initiates a write operation by generating a start condition (S), followed by the TUSB1004 7-bit address and a zero-value “W/R” bit to indicate a write cycle.
2. The TUSB1004 acknowledges the address cycle.
3. The controller presents the register offset within TUSB1004 to be written, consisting of one byte of data, MSB-first.
4. The TUSB1004 acknowledges the register offset cycle.
5. The controller terminates the write operation by generating a stop condition (P).