ZHCSGH5D August 2017 – May 2019 TUSB1042I
PRODUCTION DATA.
Each of the TUSB1042I receiver lanes has individual controls for receiver equalization. The receiver equalization gain value can be controlled either through I2C registers or through GPIOs. Table 5 details the gain value for each available combination when TUSB1042I is in GPIO mode. These same options are also available in I2C mode by updating registers EQ1_SEL, EQ2_SEL, and SSEQ_SEL.
| Equalization Setting # | USB3.1 DOWNSTREAM FACING PORTS | USB 3.1 UPSTREAM FACING PORT | ||||
|---|---|---|---|---|---|---|
| EQ1 PIN LEVEL | EQ0 PIN LEVEL | EQ GAIN at 5 GHz (dB) | SSEQ1 PIN LEVEL | SSEQ0 PIN LEVEL | EQ GAIN at 5 GHz (dB) | |
| 0 | 0 | 0 | -3.9 | 0 | 0 | -1.8 |
| 1 | 0 | R | -1.7 | 0 | R | 0.2 |
| 2 | 0 | F | -0.1 | 0 | F | 1.7 |
| 3 | 0 | 1 | 1.4 | 0 | 1 | 3.2 |
| 4 | R | 0 | 2.4 | R | 0 | 4.2 |
| 5 | R | R | 3.5 | R | R | 5.3 |
| 6 | R | F | 4.4 | R | F | 6.1 |
| 7 | R | 1 | 5.2 | R | 1 | 7.0 |
| 8 | F | 0 | 5.9 | F | 0 | 7.7 |
| 9 | F | R | 6.6 | F | R | 8.3 |
| 10 | F | F | 7.1 | F | F | 8.8 |
| 11 | F | 1 | 7.6 | F | 1 | 9.3 |
| 12 | 1 | 0 | 8.0 | 1 | 0 | 9.7 |
| 13 | 1 | R | 8.5 | 1 | R | 10.1 |
| 14 | 1 | F | 8.8 | 1 | F | 10.4 |
| 15 | 1 | 1 | 9.2 | 1 | 1 | 10.8 |