ZHCSGH5D August   2017  – May 2019 TUSB1042I

PRODUCTION DATA.  

  1. 特性
  2. 应用
  3. 说明
    1.     Device Images
      1.      简化电路原理图
      2.      TUSB1042I 眼图
  4. 修订历史记录
  5. Pin Configuration and Functions
    1.     Pin Functions
  6. Specifications
    1. 6.1  Absolute Maximum Ratings
    2. 6.2  ESD Ratings
    3. 6.3  Recommended Operating Conditions
    4. 6.4  Thermal Information
    5. 6.5  Power Supply Characteristics
    6. 6.6  DC Electrical Characteristics
    7. 6.7  AC Electrical Characteristics
    8. 6.8  DCI Specific Electrical Characteristics
    9. 6.9  Timing Requirements
    10. 6.10 Switching Characteristics
    11. 6.11 Typical Characteristics
  7. Parameter Measurement Information
  8. Detailed Description
    1. 8.1 Overview
    2. 8.2 Functional Block Diagram
    3. 8.3 Feature Description
      1. 8.3.1 USB 3.1
      2. 8.3.2 4-level Inputs
      3. 8.3.3 Receiver Linear Equalization
    4. 8.4 Device Functional Modes
      1. 8.4.1 Device Configuration in GPIO Mode
      2. 8.4.2 Device Configuration In I2C Mode
      3. 8.4.3 Linear EQ Configuration
      4. 8.4.4 USB3.1 Modes
      5. 8.4.5 Operation Timing – Power Up
    5. 8.5 Programming
    6. 8.6 Register Maps
      1. 8.6.1 General Register (address = 0x0A) [reset = 00000001]
        1. Table 9. General Registers
      2. 8.6.2 USB3.1 Control/Status Registers (address = 0x20) [reset = 00000000]
        1. Table 10. USB3.1 Control/Status Registers (0x20)
      3. 8.6.3 USB3.1 Control/Status Registers (address = 0x21) [reset = 00000000]
        1. Table 11. USB3.1 Control/Status Registers (0x21)
      4. 8.6.4 USB3.1 Control/Status Registers (address = 0x22) [reset = 00000100]
        1. Table 12. USB3.1 Control/Status Registers (0x22)
  9. Application and Implementation
    1. 9.1 Application Information
    2. 9.2 Typical Application
      1. 9.2.1 Design Requirements
      2. 9.2.2 Detailed Design Procedure
      3. 9.2.3 Application Curve
    3. 9.3 System Examples
      1. 9.3.1 USB 3.1
  10. 10Power Supply Recommendations
  11. 11Layout
    1. 11.1 Layout Guidelines
    2. 11.2 Layout Example
  12. 12器件和文档支持
    1. 12.1 相关链接
    2. 12.2 接收文档更新通知
    3. 12.3 社区资源
    4. 12.4 商标
    5. 12.5 静电放电警告
    6. 12.6 Glossary
  13. 13机械、封装和可订购信息

封装选项

机械数据 (封装 | 引脚)
散热焊盘机械数据 (封装 | 引脚)
订购信息

Layout Guidelines

  1. RXP/N and TXP/N pairs should be routed with controlled 90-Ω differential impedance (±15%).
  2. Keep away from other high speed signals.
  3. Intra-pair routing should be kept to within 2 mils.
  4. Length matching should be near the location of mismatch.
  5. Each pair should be separated at least by 3 times the signal trace width.
  6. The use of bends in differential traces should be kept to a minimum. When bends are used, the number of left and right bends should be as equal as possible and the angle of the bend should be ≥ 135 degrees. This will minimize any length mismatch causes by the bends and therefore minimize the impact bends have on EMI.
  7. Route all differential pairs on the same of layer.
  8. The number of vias should be kept to a minimum. It is recommended to keep the vias count to 2 or less.
  9. Keep traces on layers adjacent to ground plane.
  10. Do not route differential pairs over any plane split.
  11. Adding Test points will cause impedance discontinuity, and therefore, negatively impact signal performance. If test points are used, they should be placed in series and symmetrically. They must not be placed in a manner that causes a stub on the differential pair.