ZHCSGH5D August   2017  – May 2019 TUSB1042I

PRODUCTION DATA.  

  1. 1 特性
  2. 2 应用
  3. 3 说明
    1.     Device Images
      1.      简化电路原理图
      2.      TUSB1042I 眼图
  4. 4 修订历史记录
  5. 5 Pin Configuration and Functions
    1.     Pin Functions
  6. 6 Specifications
    1. 6.1  Absolute Maximum Ratings
    2. 6.2  ESD Ratings
    3. 6.3  Recommended Operating Conditions
    4. 6.4  Thermal Information
    5. 6.5  Power Supply Characteristics
    6. 6.6  DC Electrical Characteristics
    7. 6.7  AC Electrical Characteristics
    8. 6.8  DCI Specific Electrical Characteristics
    9. 6.9  Timing Requirements
    10. 6.10 Switching Characteristics
    11. 6.11 Typical Characteristics
  7. 7 Parameter Measurement Information
  8. 8 Detailed Description
    1. 8.1 Overview
    2. 8.2 Functional Block Diagram
    3. 8.3 Feature Description
      1. 8.3.1 USB 3.1
      2. 8.3.2 4-level Inputs
      3. 8.3.3 Receiver Linear Equalization
    4. 8.4 Device Functional Modes
      1. 8.4.1 Device Configuration in GPIO Mode
      2. 8.4.2 Device Configuration In I2C Mode
      3. 8.4.3 Linear EQ Configuration
      4. 8.4.4 USB3.1 Modes
      5. 8.4.5 Operation Timing – Power Up
    5. 8.5 Programming
    6. 8.6 Register Maps
      1. 8.6.1 General Register (address = 0x0A) [reset = 00000001]
        1. Table 9. General Registers
      2. 8.6.2 USB3.1 Control/Status Registers (address = 0x20) [reset = 00000000]
        1. Table 10. USB3.1 Control/Status Registers (0x20)
      3. 8.6.3 USB3.1 Control/Status Registers (address = 0x21) [reset = 00000000]
        1. Table 11. USB3.1 Control/Status Registers (0x21)
      4. 8.6.4 USB3.1 Control/Status Registers (address = 0x22) [reset = 00000100]
        1. Table 12. USB3.1 Control/Status Registers (0x22)
  9. 9 Application and Implementation
    1. 9.1 Application Information
    2. 9.2 Typical Application
      1. 9.2.1 Design Requirements
      2. 9.2.2 Detailed Design Procedure
      3. 9.2.3 Application Curve
    3. 9.3 System Examples
      1. 9.3.1 USB 3.1
  10. 10Power Supply Recommendations
  11. 11Layout
    1. 11.1 Layout Guidelines
    2. 11.2 Layout Example
  12. 12器件和文档支持
    1. 12.1 相关链接
    2. 12.2 接收文档更新通知
    3. 12.3 社区资源
    4. 12.4 商标
    5. 12.5 静电放电警告
    6. 12.6 Glossary
  13. 13机械、封装和可订购信息

封装选项

机械数据 (封装 | 引脚)
散热焊盘机械数据 (封装 | 引脚)
订购信息

5 Pin Configuration and Functions

RNQ Package
40-Pin (WQFN)
Top View

Pin Functions

PIN I/O DESCRIPTION
NAME NO.
RX1n 31 Diff I/O Differential negative input for USB3.1 Downstream Facing port.
RX1p 30 Diff I/O Differential positive input for USB3.1 Downstream Facing port.
TX1n 34 Diff O Differential negative output for USB3.1 downstream facing port.
TX1p 33 Diff O Differential positive output for USB 3.1 downstream facing port.
TX2p 37 Diff O Differential positive output for USB 3.1 downstream facing port.
TX2n 36 Diff O Differential negative output for USB 3.1 downstream facing port.
RX2p 40 Diff I/O Differential positive input for USB3.1 Downstream Facing port.
RX2n 39 Diff I/O Differential negative input for USB3.1 Downstream Facing port.
SSTXp 8 Diff I Differential positive input for USB3.1 upstream facing port.
SSTXn 7 Diff I Differential negative input for USB3.1 upstream facing port.
SSRXp 5 Diff O Differential positive output for USB3.1 upstream facing port.
SSRXn 4 Diff O Differential negative output for USB3.1 upstream facing port.
EQ1 35 4 Level I This pin along with EQ0 sets the USB receiver equalizer gain for downstream facing RX1 and RX2 when USB used.
EQ0 38 4 Level I This pin along with EQ1 sets the USB receiver equalizer gain for downstream facing RX1 and RX2 when USB used.
DCI_DAT 29(1) I/O
(PD)		 When I2C_EN ! = 0, this pin functions as DCI data output Leave open if not used.
DCI_CLK 32(1) I/O
(PD)		 When I2C_EN ! = 0, this pin functions as DCI clock output Leave open if not used.
I2C_EN 17 4 Level I I2C Programming Mode or GPIO Programming Select. I2C is only disabled when this pin is ‘0".
0 = GPIO mode (I2C disabled)
R = TI Test Mode (I2C enabled at 3.3 V)
F = I2C enabled at 1.8 V
1 = I2C enabled at 3.3 V.
A1 14 4 Level I When I2C_EN is not ‘0’, this pin will set the TUSB1042I I2C address.
SSEQ1 3 4 Level I Along with SSEQ0, sets the USB receiver equalizer gain for upstream facing SSTXP/N.
SSEQ0/A0 11 4 Level I Along with SSEQ1, sets the USB receiver equalizer gain for upstream facing SSTXP/N. When I2C_EN is not ‘0’, this pin will also set the TUSB1042I I2C address. If I2C_EN = “F”, then this pin must be set to “F” or “0”.
FLIP/SCL 21 2 Level I When I2C_EN=’0’ this is Flip control pin, otherwise this pin is I2C clock. . When used for I2C clock pullup to I2C master's VCC I2C supply.
CTL0/SDA 22 2 Level I When I2C_EN=’0’ this is a USB3.1 Switch control pin, otherwise this pin is I2C data. When used for I2C data pullup to I2C master's VCC I2C supply.
RSVD1 - 12 9, 10, 12, 13, 15, 16, 18, 19, 24, 25, 26, 27 RSVD Reserved. Leave open.
TEST1 23 2 Level I
(Failsafe)
(PD)		 Test pin. Pull down to GND.
TEST2 2 4 Level I Test pin. Leave open.
VCC 1, 6, 20, 28 P 3.3-V Power Supply
Thermal Pad G Ground
(1) Not a fail-safe I/O. Actively driving pin high while VCC is removed results in leakage voltage on VCC pins.
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