ZHCSGQ4 September 2017 TUSB213-Q1
PRODUCTION DATA.
7 Detailed Description
7.1 Overview
The TUSB213-Q1 is a USB High-Speed (HS) signal conditioner, designed to compensate for ISI signal loss in a transmission channel. TUSB213-Q1 has a patent-pending design which is agnostic to USB Low Speed (LS) and Full Speed (FS) signals and does not alter their signal characteristics, while HS signals are compensated. In addition, the design is compatible with USB On-The-Go (OTG) and Battery Charging (BC) specifications.
Programmable signal AC boost through an external resistor on EQ pin permits fine tuning device performance to optimize signals helping to pass USB HS electrical compliance tests at the connector. Additional DC Boost configurable by three level input DC_BOOST pin helps overcoming the cable losses.
7.2 Functional Block Diagram
7.3 Feature Description
7.3.1 EQ
The EQ pin of the TUSB213-Q1 is used to configure the AC boost of the device. The four levels of AC boost are set through different values of an external pulldown resistor at this pin.
7.3.2 DC BOOST
The DC_BOOST pin of the TUSB213-Q1 is a tri-level pin, used to set the DC gain of the device according to Table 1.
Table 1. DC Boost Settings
| DC BOOST SETTING VIA PIN STRAP | |
|---|---|
| DC_BOOST | DC Boost Setting (mV) |
| VIL | 40 |
| VIM | 60 |
| VIH | 80 |
7.4 Device Functional Modes
7.4.1 Low Speed (LS) Mode
TUSB213-Q1 automatically detects a LS connection and does not enable signal compensation. CD pin is asserted high.
7.4.2 Full Speed (FS) Mode
TUSB213-Q1 automatically detects a FS connection and does not enable signal compensation. CD pin is asserted high.
7.4.3 High Speed (HS) Mode
TUSB213-Q1 automatically detects a HS connection and will enable signal compensation as determined by the configuration of the DC_BOOST pin and the external pulldown resistance on its EQ pin. CD pin asserted high.
7.4.4 Shutdown Mode
TUSB213-Q1 is disabled when its RSTN pin is asserted low. In shutdown mode, the USB channel is still fully operational but there is neither signal compensation nor any indication from the CD pin as to the status of the channel.
7.4.5 I2C Mode
TUSB213-Q1 support 100 kHz I2C for device configuration, status readback and test purposes. This controller is enabled after SCL and SDA pins are sampled high shortly after de-assertion of RSTN. In this mode, the register as described in Table 2 can be accessed by I2C read/write transaction to 7-bit slave address 0x2C. It is necessary to set CFG_ACTIVE bit and reset it to zero after making changes to the EQ and DC Boost level registers to restart the state machine.
NOTE
All registers or fields in Table 2 which are not specifically mentioned are considered reserved. The default value of these reserved registers or fields must not be changed. It is suggested to perform a read-modify-write operation to maintain the default value of the reserved fields.
Table 2. Register definition
| Offset | Bit(s) | Name | Type | Default | Description |
|---|---|---|---|---|---|
| 0x01 | 6:4 | ACB_LVL | RW | XXX (Sampled from EQ pin at reset) |
Sets the level of AC boost 000 :Level 0 AC boost programmed [MIN] 001 : Level 1 AC boost programmed 011 : Level 2 AC boost programmed 111 : Level 3 AC boost programmed [MAX] |
| 0x03 | 0 | CFG_ACTIVE | RW | 1b |
Configuration mode 0 : Normal mode. State machine enabled. 1 : Configuration mode: State machine disabled. After reset, if I2C mode is true (SCL and SDA are both pulled high) it is maintained until it is cleared by an I2C write, but, if I2C mode is not true, it is cleared automatically. |
| 0x0E | 2:0 | DCB_LVL | RW | XXX (Sampled from DC_BOOST pin at reset) |
Sets the level of DC Boost 011 : 40mV (DC_Boost = L) 101 : 60mV (DC_Boost = M, default) 111 : 80mV (DC_Boost = H) |