ZHCSNF8A March   2021  – December 2023 TUSB216I

PRODUCTION DATA  

  1.   1
  2. 1 特性
  3. 2 应用
  4. 3 说明
  5. 4 Device Comparison
  6. 5 Pin Configuration and Functions
  7. 6 Specifications
    1. 6.1 Absolute Maximum Ratings
    2. 6.2 ESD Ratings
    3. 6.3 Recommended Operating Conditions
    4. 6.4 Thermal Information
    5. 6.5 Electrical Characteristics
    6. 6.6 Switching Characteristics
    7. 6.7 Timing Requirements
  8. 7 Detailed Description
    1. 7.1 Overview
    2. 7.2 Functional Block Diagram
    3. 7.3 Feature Description
      1. 7.3.1 High-Speed Boost
      2. 7.3.2 RX Sensitivity
    4. 7.4 Device Functional Modes
      1. 7.4.1 Low-Speed (LS) Mode
      2. 7.4.2 Full-Speed (FS) Mode
      3. 7.4.3 High-Speed (HS) Mode
      4. 7.4.4 High-Speed Downstream Port Electrical Compliance Test Mode
      5. 7.4.5 Shutdown Mode
      6. 7.4.6 I2C Mode
      7. 7.4.7 BC 1.2 Battery Charging Controller
    5. 7.5 TUSB216 Registers
  9. 8 Application and Implementation
    1. 8.1 Application Information
    2. 8.2 Typical Application
      1. 8.2.1 Design Requirements
      2. 8.2.2 Detailed Design Procedure
        1. 8.2.2.1 Test Procedure to Construct USB High-speed Eye Diagram
          1. 8.2.2.1.1 For a Host Side Application
          2. 8.2.2.1.2 For a Device Side Application
      3. 8.2.3 Application Curves
    3. 8.3 Power Supply Recommendations
    4. 8.4 Layout
      1. 8.4.1 Layout Guidelines
      2. 8.4.2 Layout Example
  10. 9 Device and Documentation Support
    1. 9.1 接收文档更新通知
    2. 9.2 支持资源
    3. 9.3 Trademarks
    4. 9.4 静电放电警告
    5. 9.5 术语表
  11. 10Revision History
  12. 11Mechanical, Packaging, and Orderable Information

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机械数据 (封装 | 引脚)
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订购信息

5 Pin Configuration and Functions

GUID-20210303-CA0I-PZ9K-BGD2-858QK2XFWJGD-low.svg Figure 5-1 TUSB216I RWB Package, 12-Pin X2QFN (Top View)
Table 5-1 Pin Functions
PIN TYPE(1) INTERNAL
PULLUP/PULLDOWN		 DESCRIPTION
NAME NO.
BOOST 6 I N/A USB High-speed boost select via external pull down resistor.
Both edge boost and DC boost are controlled by a single pin in non-I2C mode. In I2C mode edge boost and DC boost can be individually controlled.
Sampled upon power up. Does not recognize real time adjustments.
Auto selects BOOST LEVEL = 3 when left floating.
CDP_ENZ 11 I 500 kΩ PU
Set CDP_ENZ is low to enable BC 1.2 CDP controller
RX_SEN(3)/ENA_HS 9 I/O N/A In I2C mode:
Reserved for TI test purpose.
In non-I2C mode:
At reset: 3-level input signal RX_SEN. USB High-speed RX Sensitivity Setting to Compensate ISI Jitter
H (pin is pulled high) – high RX sensitivity (high loss channel)
M (pin is left floating) – medium RX sensitivity (medium loss channel)
L (pin is pulled low) – low RX sensitivity (low loss channel)
After reset: Output signal ENA_HS. Flag indicating that channel is in High-speed mode. Asserted upon:
1. Detection of USB-IF High-speed test fixture from an unconnected state followed by transmission of USB TEST_PACKET pattern.
2. Squelch detection following USB reset with a successful HS handshake [HS handshake is declared to be successful after single chirp J chirp K pair where each chirp is within 18 μs – 128 μs].
D2P 7 I/O N/A USB High-speed positive port.
D2M 8 I/O N/A USB High-speed negative port.
GND 10 P N/A Ground
D1M 1 I/O N/A USB High-speed negative port..
D1P 2 I/O N/A USB High-speed positive port.
SDA(2) 3 I/O 500 kΩ PU
1.8 MΩ PD		 I2C Mode:
Bidirectional I2C data pin [7-bit I2C slave address = 0x2C].
In non I2C mode:
Reserved for TI test purpose.
VCC 12 P N/A Supply power
RSTN 5 I 500 kΩ PU
1.8 MΩ PD		 Device disable/enable.
Low – Device is at reset and in shutdown, and
High - Normal operation.
Recommend 0.1-µF external capacitor to GND to ensure clean power on reset if not driven. If the pin is driven, it must be held low until the supply voltage for the device reaches within specifications.
SCL(2)/CD 4 I/O When RSTN asserted there is a 500 kΩ PD In I2C mode:
I2C clock pin [I2C address = 0x2C].
Non I2C mode:
After reset: Output CD. Flag indicating that a USB device is attached (connection detected). Asserted from an unconnected state upon detection of DP or DM pull-up resistor. De-asserted upon detection of disconnect.
(1) I = input, O = output, P = power
(2) Pull-up resistors for SDA and SCL pins in I2C mode should be RPull-up (depending on I2C bus voltage). If both SDA and SCL are pulled up at power-up the device enters into I2C mode.
(3) Pull-down and pull-up resistors for RX_SEN pin must follow RRXSEN1 and RRXSEN2 resistor recommendations in non I2C mode.
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