TUSB217A-Q1 supports 100 KHz I2C for device configuration, status read back and test purposes. For detail electrical and functional specifications refer to I2C Bus Specification 2.1, 2001 – STANDARD MODE. This controller is enabled after SCL and SDA pins are sampled high shortly after return from shutdown. In this mode, the CSR can be accessed by I2C read/write transaction to 7-bit slave address 0x2C. It is advised to set CFG_ACTIVE bit before changing values. This halts the FSM, and reset it after all changes are made. This ensure proper startup into high-speed mode.