ZHCSDY5C July 2015 – July 2024 TUSB4041I-Q1
PRODUCTION DATA
For this design example, use the parameters listed in Table 7-1.
DESIGN PARAMETER | EXAMPLE VALUE |
---|---|
VDD supply | 1.1 V |
VDD33 supply | 3.3 V |
Upstream port USB support (HS, FS) | HS, FS |
Downstream port 1 USB support (HS, FS, LS) | HS, FS, LS |
Downstream port 2 USB support (HS, FS, LS) | HS, FS, LS |
Downstream port 3 USB support (HS, FS, LS) | HS, FS, LS |
Downstream port 4 USB support (HS, FS, LS) | HS, FS, LS |
Number of removable downstream ports | 4 |
Number of non-removable downstream ports | 0 |
Full power management of downstream ports | Yes (FULLPWRMGMTZ = 0) |
Individual control of downstream port power switch | Yes (GANGED = 0) |
Power switch enable polarity | Active high (PWRCTL_POL = 1) |
Battery charge support for downstream port 1 | Yes |
Battery charge support for downstream port 2 | Yes |
Battery charge support for downstream port 3 | Yes |
Battery charge support for downstream port 4 | Yes |
I2C EEPROM support | No |
24-MHz clock source | Crystal |