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ZHCSDY5C July 2015 – July 2024 TUSB4041I-Q1

PRODUCTION DATA

封装选项

机械数据 (封装 | 引脚)

PAP|64
- MPQF071C

散热焊盘机械数据 (封装 | 引脚)

PAP|64
- PPTD310A

订购信息

5.6 Power-Up Timing Requirements

		MIN	MAX	UNIT
t_d1	VDD33 stable before VDD stable⁽¹⁾	See ⁽²⁾		ms
t_d2	VDD and VDD33 stable before deassertion of GRSTz	3		ms
t_{su_io}	Setup for MISC inputs⁽³⁾ sampled at the deassertion of GRSTz	0.1		µs
t_{hd_io}	Hold for MISC inputs⁽³⁾ sampled at the deassertion of GRSTz	0.1		µs
t_{VDD33_RAMP}	VDD33 supply ramp requirements	0.2	100	ms
t_{VDD_RAMP}	VDD supply ramp requirements	0.2	100	ms

(1) An active reset is required if the VDD33 supply is stable before the VDD11 supply. This active Reset shall meet the 3ms power-up delay counting from both power supplies being stable to the de-assertion of GRSTz.

(2) The VDD33 and VDD have no power-on relationship unless GRSTz is only connected to a capacitor to GND. Then VDD must be stable minimum of 10 μs before the VDD33.

(3) MISC pins sampled at de-assertion of GRSTz: FULLPWRMGMTz, GANGED, PWRCTL_POL, SMBUSz, BATEN[4:1], and AUTOENz.

TUSB4041I-Q1 Power-Up Timing Requirements

Figure 5-1 Power-Up Timing Requirements