ZHCSFQ2C November   2016  – June 2018 TUSB422

PRODUCTION DATA.  

  1. 1 特性
  2. 2 应用
  3. 3 说明
    1.     Device Images
      1.      简化电路原理图
      2.      USB Type-C 智能手机
  4. 4 修订历史记录
  5. 5 Pin Configuration and Functions
    1.     Pin Functions
  6. 6 Specifications
    1. 6.1 Absolute Maximum Ratings
    2. 6.2 ESD Ratings
    3. 6.3 Recommended Operating Conditions
    4. 6.4 Thermal Information
    5. 6.5 Electrical Characteristics
    6. 6.6 Timing Requirements
    7. 6.7 Typical Characteristics
  7. 7 Detailed Description
    1. 7.1 Overview
    2. 7.2 Functional Block Diagram
      1. 7.2.1 Cables, Adapters, and Direct Connect Devices
        1. 7.2.1.1 USB Type-C receptacles and Plugs
        2. 7.2.1.2 USB Type-C Cables
        3. 7.2.1.3 Direct Connect Devices
    3. 7.3 Feature Description
      1. 7.3.1  USB PD I2C Type-C Port Controller Interface (TCPC)
      2. 7.3.2  USB PD BMC PHY
      3. 7.3.3  DFP (Downstream Facing Port)
      4. 7.3.4  UFP (Upstream Facing Port)
      5. 7.3.5  DRP (Dual-Role Port)
      6. 7.3.6  Type-C Current Mode Advertising
      7. 7.3.7  VBUS Source Enable/Disable Control
      8. 7.3.8  VBUS Sink Enable/Disable Control
      9. 7.3.9  VBUS Monitoring
      10. 7.3.10 VBUS Discharge
      11. 7.3.11 VBUS to CC Short Detection from Legacy Charger
      12. 7.3.12 VBUS Power Source Requirements
      13. 7.3.13 VBUS Power Sink Requirements.
      14. 7.3.14 VCONN
      15. 7.3.15 Interrupts
      16. 7.3.16 Fast Role Swap
    4. 7.4 Device Functional Modes
      1. 7.4.1 Unattached Mode
      2. 7.4.2 Active Mode
      3. 7.4.3 Power Role Swap
      4. 7.4.4 Debug Accessory
      5. 7.4.5 Dead Battery Mode
    5. 7.5 Programming
    6. 7.6 Register Maps
      1. 7.6.1  CSR Registers
      2. 7.6.2  Vendor ID Byte 0 Register (address = 0x00) [reset = 0x51]
        1. Table 7. Vendor ID Byte 0 Register Field Descriptions
      3. 7.6.3  Vendor ID Byte 1 Register (address = 0x01) [reset = 0x04]
        1. Table 8. Vendor ID Byte 1 Register Field Descriptions
      4. 7.6.4  Product ID Byte 0 Register (address = 0x02) [reset = 0x22]
        1. Table 9. Product ID Byte 0 Register Field Descriptions
      5. 7.6.5  Product ID Byte 1 Register (address = 0x03) [reset = 0x04]
        1. Table 10. Product ID Byte 1 Register Field Descriptions
      6. 7.6.6  Device ID Byte 0 Register (address = 0x04) [reset = 0x00]
        1. Table 11. Device ID Byte 0 Register Field Descriptions
      7. 7.6.7  Device ID Byte 1 Register (address = 0x05) [reset = 0x01]
        1. Table 12. Device ID Byte 1 Register Field Descriptions
      8. 7.6.8  USB Type-C Revision Byte 0 Register (address = 0x06) [reset = 0x11]
        1. Table 13. USB Type-C Revision Byte 0 Register Field Descriptions
      9. 7.6.9  USB Type-C Revision Byte 1 Register (address = 0x07) [reset = 0x00]
        1. Table 14. USB Type-C Revision Byte 1 Descriptions
      10. 7.6.10 USB PD Revision Version Byte 0 Register (address = 0x08) [reset = 0x11]
        1. Table 15. USB PD Revision Version Byte 0 Descriptions
      11. 7.6.11 USB PD Revision Version Byte 1 Register (address = 0x09) [reset = 0x20]
        1. Table 16. USB PD Revision Version Byte 1 Descriptions
      12. 7.6.12 PD Interface Revision Byte 0 Register (address = 0x0A) [reset = 0x10]
        1. Table 17. PD Interface Revision Byte 0 Descriptions
      13. 7.6.13 PD Interface Revision Byte 1 Register (address = 0x0B) [reset = 0x10]
        1. Table 18. PD Interface Revision Byte 1 Descriptions
      14. 7.6.14 Alert Byte 0 Register (address = 0x10) [reset = 0x00]
        1. Table 19. Alert Byte 0 Register Descriptions
      15. 7.6.15 Alert Byte 1 Register (address = 0x11) [reset = 0x00]
        1. Table 20. Alert Byte 1 Register Descriptions
      16. 7.6.16 Alert Mask Byte 0 Register (address = 0x12) [reset = 0xFFh]
        1. Table 21. Alert Mask Byte 0 Register Descriptions
      17. 7.6.17 Alert Mask Byte 1 Register (address = 0x13) [reset = 0x0F]
        1. Table 22. Alert Mask Byte 1 Register Descriptions
      18. 7.6.18 Power Status Mask Register (address = 0x14) [reset = 0xFF]
        1. Table 23. Power Status Mask Register Descriptions
      19. 7.6.19 FAULT Status Mask Register (address = 0x15) [reset = 0x7F]
        1. Table 24. FAULT Status Mask Register Descriptions
      20. 7.6.20 Config Standard Output Register (address = 0x18) [reset = 0x60]
        1. Table 25. Config Standard Output Descriptions
      21. 7.6.21 TCPC Control Register (address = 0x19) [reset = 0x00]
        1. Table 26. TCPC Control Register Descriptions
      22. 7.6.22 ROLE Control Register (address = 0x1A) [reset = 0x0A]
        1. Table 27. ROLE Control Register Descriptions
      23. 7.6.23 FAULT Control Register (address = 0x1B) [reset = 0x06]
        1. Table 28. FAULT Control Register Descriptions
      24. 7.6.24 Power Control Register (address = 0x1C) [reset = 0x60]
        1. Table 29. Power Control Register Descriptions
      25. 7.6.25 CC Status Register (address = 0x1D) [reset = 0x00]
        1. Table 30. CC Status Register Descriptions
      26. 7.6.26 Power Status Register (address = 0x1E) [reset = 0x00]
        1. Table 31. Power Status Register Descriptions
      27. 7.6.27 Fault Status Register (address = 0x1F) [reset = 0x00]
        1. Table 32. Fault Status Register Descriptions
      28. 7.6.28 Command Register (address = 0x23) [reset = 0x00]
        1. Table 33. Command Register Descriptions
      29. 7.6.29 Device Capabilities 1 Byte 0 Register (address = 0x24) [reset = 0x98]
        1. Table 34. Device Capabilities 1 Byte 0 Descriptions
      30. 7.6.30 Device Capabilities 1 Byte 1 Register (address = 0x25) [reset = 0x1E]
        1. Table 35. Device Capabilities 1 Byte 1 Descriptions
      31. 7.6.31 Device Capabilities 2 Byte 0 Register (address = 0x26) [reset = 0xC5]
        1. Table 36. Device Capabilities 2 Byte 0 Register Descriptions
      32. 7.6.32 Device Capabilities 2 Byte 1 Register (address = 0x27) [reset = 0x00]
        1. Table 37. Device Capabilities 2 Byte 1 Register Descriptions
      33. 7.6.33 Standard Input Capabilities Register (address = 0x28) [reset = 0x00]
        1. Table 38. Standard Input Capabilities Register Descriptions
      34. 7.6.34 Standard Output Capabilities Register (address = 0x29) [reset = 0x00]
        1. Table 39. Standard Output Capabilities Register Descriptions
      35. 7.6.35 Message Header Info Register (address = 0x2E) [reset = 0x02]
        1. Table 40. Message Header Info Register Descriptions
      36. 7.6.36 Receiver Detect Register (address = 0x2F) [reset = 0x00]
        1. Table 41. Receiver Detect Register Descriptions
      37. 7.6.37 Receive Byte Count Register (address = 0x30) [reset = 0x00]
        1. Table 42. Receive Byte Count Register Descriptions
      38. 7.6.38 Receive Buffer Frame Type Register (address = 0x31) [reset = 0x00]
        1. Table 43. Receive Buffer Frame Type Register Descriptions
      39. 7.6.39 Receive Buffer Header Byte 0 Register (address = 0x32) [reset = 0x00]
        1. Table 44. Receive Buffer Header Byte 0 Descriptions
      40. 7.6.40 Receive Buffer Header Byte 1 Register (address = 0x33) [reset = 0x00]
        1. Table 45. Receive Buffer Header Byte 1 Descriptions
      41. 7.6.41 Receive Buffer Data Object 1 Through 7 Register (address = 0x34 through 0x4F) [reset = 0x00]
        1. Table 46. Receive Buffer Data Object 1 Through 7 Descriptions
      42. 7.6.42 Transmit Register (address = 0x50) [reset = 0x00]
        1. Table 47. Transmit Register Descriptions
      43. 7.6.43 Transmit Byte Count Register (address = 0x51) [reset = 0x00]
        1. Table 48. Transmit Byte Count Register Descriptions
      44. 7.6.44 Transmit Buffer Header Byte 0 Register (address = 0x52) [reset = 0x00]
        1. Table 49. Transmit Buffer Header Byte 0 Register Descriptions
      45. 7.6.45 Transmit Buffer Header Byte 1 Register (address = 0x53) [reset = 0x00]
        1. Table 50. Transmit Buffer Header Byte 1 Register Descriptions
      46. 7.6.46 Transmit Buffer Data Object 1 Through 7 Register (address = 0x54 through 0x6F) [reset = 0x00]
        1. Table 51. Transmit Buffer Data Object 1 Through 7 Register Descriptions
      47. 7.6.47 VBUS Voltage Byte 0 Register (address = 0x70) [reset = 0x00]
        1. Table 52. VBUS Voltage Byte 0 Descriptions
      48. 7.6.48 VBUS Voltage Byte 1 Register (address = 0x71) [reset = 0x00]
        1. Table 53. VBUS Voltage Byte 1 Register Descriptions
      49. 7.6.49 VBUS Sink Disconnect Threshold Byte 0 Register (address = 0x72) [reset = 0x00]
        1. Table 54. VBUS Sink Disconnect Threshold Byte 0 Register Descriptions
      50. 7.6.50 VBUS Sink Disconnect Threshold Byte 1 Register (address = 0x73) [reset = 0x00]
        1. Table 55. VBUS Sink Disconnect Threshold Byte 1 Register Descriptions
      51. 7.6.51 VBUS Stop Discharge Threshold Byte 0 Register (address = 0x74) [reset = 0x00]
        1. Table 56. VBUS Stop Discharge Threshold Byte 0 Register Descriptions
      52. 7.6.52 VBUS Stop Discharge Threshold Byte 1 Register (address = 0x75) [reset = 0x00]
        1. Table 57. VBUS Stop Discharge Threshold Byte 1 Register Descriptions
      53. 7.6.53 VBUS Voltage Alarm High Config Byte 0 Register (address = 0x76) [reset = 0x00]
        1. Table 58. VBUS Voltage Alarm High Config Byte 0 Register Descriptions
      54. 7.6.54 VBUS Voltage Alarm High Config Byte 1 Register (address = 0x77) [reset = 0x00]
        1. Table 59. VBUS Voltage Alarm High Config Byte 1 Register Descriptions
      55. 7.6.55 VBUS Voltage Alarm Low Config Byte 0 Register (address = 0x78) [reset = 0x00]
        1. Table 60. VBUS Voltage Alarm Low Config Byte 0 Register Descriptions
      56. 7.6.56 VBUS Voltage Alarm Low Config Byte 1 Register (address = 0x79) [reset = 0x00]
        1. Table 61. VBUS Voltage Alarm Low Config Byte 1 Register Descriptions
      57. 7.6.57 Vendor Interrupts Status Register (address = 0x90) [reset = 0x00]
        1. Table 62. Vendor Interrupts Status Register Descriptions
      58. 7.6.58 Vendor Interrupts Mask Register (address = 0x92) [reset = 0x00]
        1. Table 63. Vendor Interrupts Mask Register Descriptions
      59. 7.6.59 CC General Control Register (address = 0x94) [reset = 0x04]
        1. Table 64. CC General Control Register Descriptions
      60. 7.6.60 PHY BMC TX Control Register (address = 0x95) [reset = 0x00]
        1. Table 65. PHY BMC TX Control Register Descriptions
      61. 7.6.61 PHY BMC RX Control Register (address = 0x96) [reset = 0x00]
        1. Table 66. PHY BMC RX Control Register Descriptions
      62. 7.6.62 PHY BMC RX Status Register (address = 0x97) [reset = 0x00]
        1. Table 67. PHY BMC RX Status Register Descriptions
      63. 7.6.63 VBUS and VCONN Control Register (address = 0x98) [reset = 0x00]
        1. Table 68. VBUS and VCONN Control Descriptions
      64. 7.6.64 OTSD Control Register (address = 0x99) [reset = 0x00]
        1. Table 69. OTSD Control Register Descriptions
      65. 7.6.65 LFO Timer Low Register (address = 0xA0) [reset = 0x00]
        1. Table 70. LFO Timer Low Register Descriptions
      66. 7.6.66 LFO Timer High Register (address = 0xA1) [reset = 0x00]
        1. Table 71. LFO Timer High Register Descriptions
      67. 7.6.67 Page Select Register (address = 0xFF) [reset = 0x00]
        1. Table 72. Page Select Register Descriptions
  8. 8 Application and Implementation
    1. 8.1 Application Information
    2. 8.2 Typical Application
      1. 8.2.1 Design Requirements
      2. 8.2.2 Detailed Design Procedure
      3. 8.2.3 Application Curve
  9. 9 Power Supply Recommendations
  10. 10Layout
    1. 10.1 Layout Guidelines
    2. 10.2 Layout Example
  11. 11器件和文档支持
    1. 11.1 接收文档更新通知
    2. 11.2 社区资源
    3. 11.3 商标
    4. 11.4 静电放电警告
    5. 11.5 术语表
  12. 12机械、封装和可订购信息

封装选项

请参考 PDF 数据表获取器件具体的封装图。

机械数据 (封装 | 引脚)
  • YFP|9
散热焊盘机械数据 (封装 | 引脚)
订购信息

6.5 Electrical Characteristics

over operating free-air temperature range (unless otherwise noted)
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
Power Consumption
I(UNATTACHED_UFP) UFP Current consumption in Unattached.SNK when port is unconnected and waiting for connection VDD = 3.7V 10 µA
I(UNATTACHED_DRP) DRP Current consumption while toggling between Unattached.SNK and Unattached.SRC when port is unconnected and waiting for connection. VDD = 3.7V 12 µA
I(UNATTACHED_DFP) DFP Current consumption in Unattached.SRC when port is unconnected and waiting for connection VDD = 3.7V 11 µA
I(ACTIVE_UFP) UFP Current consumption in attached.SNK Active Mode. PD Disabled. VDD = 3.7V 330 µA
I(ACTIVE_UFP_PD) UFP current consumption in attached.SNK with PD enabled and transmitting continuous BIST Carrier Mode 2. VDD = 3.7V; TX_CARRIER_MODE2_SEL = 1; 5.2 mA
CC pins (CC1 and CC2)
VCC(USB_DB) Voltage on both CC pins when in dead battery and the attached DFP is presenting default current advertisement VDD = 0V 0.25 1.5 V
VCC(MED_DB) Voltage on both CC pins when in dead battery and the attached DFP is presenting medium current (1.5A) advertisement VDD = 0V 0.45 1.5 V
VCC(HIGH_DB) Voltage on both CC pins when in dead battery and the attached DFP is presenting high current (3.0A) advertisement VDD = 0V 0.88 2.18 V
R(CC_RD) Pull-down resistor when in UFP or DRP mode VDD = 2.7V to 5.5V 4.6 5.1 5.6 kΩ
R(CC_RA) Pull-down resistor for active cable VDD = 2.7V to 5.5V 0.8 1 1.2 kΩ
ICC(LKG) Leakage current through CC pins VDD = 0V; VCONN = 0V; CC pin = 5.5V 1.36 mA
V(UFP_CC_USB) Voltage level range for detecting a DFP attach when configured as a UFP and DFP is advertising default current source capability 0.25 0.61 V
V(UFP_CC_MED) Voltage level range for detecting a DFP attach when configured as a UFP and DFP is advertising medium (1.5A) current source capability 0.7 1.16 V
V(UFP_CC_HIGH) Voltage level range for detecting a DFP attach when configured as a UFP and DFP is advertising high (3.0A) current source capability 1.31 2.04 V
VTH(DFP_CC_USB) Voltage threshold for detecting a UFP attach when TUSB422 is advertising default current source capability. 1.51 1.6 1.64 V
VTH(DFP_CC_MED) Voltage threshold for detecting a UFP attach when TUSB422 is advertising medium current (1.5A) source capability. 1.51 1.6 1.64 V
VTH(DFP_CC_HIGH) Voltage threshold for detecting a UFP attach when TUSB422 is advertising high current (3.0A) source capability. 2.46 2.6 2.74 V
VTH(AC_CC_USB) Voltage threshold for detecting a active cable attach when advertising default current 0.15 0.2 0.25 V
VTH(AC_CC_MED) Voltage threshold for detecting a active cable attach when advertising medium current 0.35 0.4 0.45 V
VTH(AC_CC_HIGH) Voltage threshold for detecting a active cable attach when advertising high current. 0.76 0.8 0.84 V
ICC(DEFAULT_P) Default mode pull-up current source when advertising default current. 64 80 96 µA
ICC(MED_P) Medium (1.5A) mode pull-up current source when advertising medium current. 166 180 194 µA
ICC(HIGH_P) High (3.0A) mode pull-up current source when advertising high current. VDD > 3.0V 304 330 356 µA
RTX(PD) Output impedance of CC1/CC2 during TX when operating in PD mode and driving the CC line. At 750KHz 33 48 75 Ω
RTX(FRS_PD) Fast Role Swap request transmit driver resistance (excluding cable resistance) 5 Ω
VOH(PD) Transmit high voltage when operating in PD mode 1.05 1.125 1.2 V
VOL(PD) Transmit low voltage when operating in PD mode. 0.07 V
RRX(PD) Receiver input impedance. Does Not include pull-up or pulldown resistance from cable detect. TX is Hi-Z 1 MΩ
VIH(PD_SRC) Input high voltage when sourcing power. Selected when POWER_ROLE = 1. 0.8925 1.5325 V
VIH(PD_SNK) Input high voltage when sinking power. Selected when POWER_ROLE = 0. 0.6425 1.5325 V
VIL(PD_SRC) Input low voltage when sourcing power. Selected when POWER_ROLE = 1. -0.3325 0.4825 V
VIL(PD_SNK) Input low voltage when sinking power. Selected when POWER_ROLE = 0. -0.3325 0.2325 V
CRX(SHUNT) External shunt capacitance on both CC1 and CC2. 200 450 pF
Control pins: INT_N
I(INTN_LEAK) INT_N leakage VDD = 0V; 0 < INT_N < 3.3V -1 1 µA
VOL Low-level signal output voltage IOL = -2mA 0.4 V
I2C (SDA and SCL). VDD must be above 3V to operate at 3.3V I2C levels
VIH(I2C) High-level input signal voltage 1.2 V
VIL(I2C) Low-level input signal voltage 0.4 V
VOL(I2C) Low-level signal output voltage (open-drain) 0.4 V
IOL(I2C) Low level output current 6 mA
I(I2C_LKG) Leakage through SDA and SCL pins VDD = 0V; pin pulled up to 3.6V -1 1 µA
C(I2C) Capacitance for SDA and SCL pins 10 pF
C(I2C_FM+_BUS) I2C bus capacitance for FM+ (1MHz) 150 pF
C(I2C_FM_BUS) I2C bus capacitance for FM (400KHz) 150 pF
R(EXT_I2C_FM+) External resistors on both SDA and SCL when operating at FM+ (1MHz) C(I2C_FM+_BUS) = 150pF 620 820 910 Ω
R(EXT_I2C_FM) External resistors on both SDA and SCL when operating at FM (400KHz) C(I2C_FM_BUS) = 150pF 620 1500 2200 Ω
VCONN
RDS(ON) ON resistance of the VCONN power FET. 0.4 0.75 Ω
V(PASS) Voltage to pass through VCONN power FET 5 V
I(VCONN) VCONN current limit; VCONN is disconnected above this voltage. 500 650 850 mA
V(VCONN_PRES) Threshold for detecting Vconn present. 2 2.4 V
C(VCONN) Bulk capacitance on VCONN; Placed on VCONN pin supply 10 200 µF
R(VCONN_DIS) Resistance to GND when Vconn discharge is enabled 4.6 5.1 5.6 KΩ
VBUSIN
C(BULK_SRC) Source External bulk capacitance when operating as VBUS Source. 10 150 µF
C(SNK) Sink External bulk capacitance on VBUS at connector 1 10 µF
C(SNKPD) Sink External bulk capacitance on VBUS after success PD negotiation 1 100 µF
R(BLEED) Resistance to gnd when bleed discharge is enabled 8 10 12.5 KΩ
V(SRCSLEWNEG) VBUS discharge maximum slew rate -30 mV/µs
V(VBUS_MEASURE_ACC) VBUS_VOLTAGE register measurement accuracy -2 2 %
OTSD
T(OTSD1) TJ over temperature trip threshold resulting in VCONN turn off and flag set. 150 °C
千亿体育app官网登录(中国)官方网站IOS/安卓通用版/手机APP | 米乐app下载官网（中国）|ios|Android/通用版APP最新版 | 米乐|米乐·M6（中国大陆）官方网站 | 千亿体育登陆地址 | 华体会体育（中国）HTH·官方网站 | 千赢qy国际_全站最新版千赢qy国际V6.2.14安卓/IOS下载 | 18新利网v1.2.5|中国官方网站 | bob电竞真人（中国官网）安卓/ios苹果/电脑版【1.97.95版下载】 | 千亿体育app官方下载(中国)官方网站IOS/安卓/手机APP下载安装 |