ZHCSEG8F December   2015  – December 2023 TUSB542

PRODUCTION DATA  

  1.   1
  2. 1 特性
  3. 2 应用
  4. 3 说明
  5. 4 Pin Configuration and Functions
  6. 5 Specifications
    1. 5.1  Absolute Maximum Ratings
    2. 5.2  ESD Ratings
    3. 5.3  Recommended Operating Conditions
    4. 5.4  Thermal Information
    5. 5.5  Electrical Characteristics, Power Supply Currents
    6. 5.6  Electrical Characteristics, DC
    7. 5.7  Electrical Characteristics, Dynamic
    8. 5.8  Electrical Characteristics, AC
    9. 5.9  Timing Requirements
    10. 5.10 Switching Characteristics
    11. 5.11 Typical Characteristics
      1. 5.11.1 1-Inch Pre Channel
      2. 5.11.2 24-Inch Pre Channel
      3. 5.11.3 32-Inch Pre Channel
  7. 6 Detailed Description
    1. 6.1 Overview
    2. 6.2 Functional Block Diagram
    3. 6.3 Feature Description
      1. 6.3.1 Receiver Equalization
      2. 6.3.2 De-Emphasis Control and Output Swing
      3. 6.3.3 Automatic LFPS Detection
      4. 6.3.4 Automatic Power Management
    4. 6.4 Device Functional Modes
      1. 6.4.1 Disconnect Mode
      2. 6.4.2 U Modes
        1. 6.4.2.1 U0 Mode
        2. 6.4.2.2 U2/U3 Mode
  8. 7 Application and Implementation
    1. 7.1 Application Information
    2. 7.2 Typical Applications, USB Type-C Port SS MUX
      1. 7.2.1 Design Requirements
      2. 7.2.2 Detailed Design Procedure
      3. 7.2.3 Application Curves
    3. 7.3 Typical Application: Switching USB SS Host or Device Ports
      1. 7.3.1 Design Requirements
      2. 7.3.2 Detailed Design Procedure
      3. 7.3.3 Application Curves
    4. 7.4 Power Supply Recommendations
    5. 7.5 Layout
      1. 7.5.1 Layout Guidelines
      2. 7.5.2 Layout Example
  9. 8 Device and Documentation Support
    1. 8.1 接收文档更新通知
    2. 8.2 支持资源
    3. 8.3 Trademarks
    4. 8.4 静电放电警告
    5. 8.5 术语表
  10. 9 Revision History
  11. 10Mechanical, Packaging, and Orderable Information

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5.6 Electrical Characteristics, DC

over operating free-air temperature range (unless otherwise noted)
PARAMETERTEST CONDITIONSMINTYPMAXUNIT
TRI-STATE CMOS INPUTS (CNFG_A1, CNFG_B1, CNFG_A2 and CNFG_B2)
VIHHigh-level input voltageVCC x 0.75V
VIMMid-level input voltageVCC / 2V
VILMid-level input voltageVCC x 0.25V
VFFloating voltageVIN = High impedanceVCC / 2V
R(PU)Internal pull-up resistance105kΩ
R(PD)Internal pull-down resistance105kΩ
IIHHigh-level input currentVIN = 1.98V26µA
IILLow-level input currentVIN = GND–26µA
IlkgExternal leakage current (from application board + Application Processor pin high impedance) toleranceVIN = GND or VIN = 1.98V–11µA
CMOS INPUT – SEL
VIHHigh-level input voltageVCC x 0.7V
VILMid-level input voltageVCC x 0.3V
IIHHigh-level input currentVIN = 1.98V5µA
IILLow-level input currentVIN = GND–16µA
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