米6体育平台手机版

ZHCSGH4B June 2017 – May 2019 TUSB546A-DCI

PRODUCTION DATA.

over operating free-air temperature range (unless otherwise noted)

PARAMETER		MIN	MAX	UNIT
AUXp or AUXn and SBU1 or SBU2
t_{AUX_PD}	Switch propagation delay		400	ps
t_{AUX_SW_OFF}	Switching time CTL1 to switch OFF. Not including TCTL1_DEBOUNCE.		500	ns
t_{AUX_SW_ON}	Switching time CTL1 to switch ON		500	ns
t_{AUX_INTRA}	Intra-pair output skew		100	ps
USB3.1 and DisplayPort mode transition requirement GPIO mode
t_{GP_USB_4DP}	Min overlap of CTL0 and CTL1 when transitioning from USB 3.1 only mode to 4-Lane DisplayPort mode or vice versa.	4		µs
CTL1 and HPDIN
t_{CTL1_DEBOUNCE}	CTL1 and HPDIN debounce time when transitioning from H to L.	2	10	ms
I²C (Refer to Figure 11)
f_SCL	I²C clock frequency		1	MHz
t_BUF	Bus free time between START and STOP conditions	0.5		µs
t_HDSTA	Hold time after repeated START condition. After this period, the first clock pulse is generated	0.26		µs
t_LOW	Low period of the I²C clock	0.5		µs
t_HIGH	High period of the I²C clock	0.26		µs
t_SUSTA	Setup time for a repeated START condition	0.26		µs
t_HDDAT	Data hold time	0		μs
t_SUDAT	Data setup time	50		ns
t_R	Rise time of both SDA and SCL signals		120	ns
t_F	Fall time of both SDA and SCL signals	20 × (V_(I2C)/5.5 V)	120	ns
t_SUSTO	Setup time for STOP condition	0.26		μs
C_b	Capacitive load for each bus line		150	pF