ZHCSGH4B June 2017 – May 2019 TUSB546A-DCI
PRODUCTION DATA.
Each of the TUSB546A-DCI receiver lanes has individual controls for receiver equalization. The receiver equalization gain value can be controlled either through I2C registers or through GPIOs. Table 7 details the gain value for each available combination when TUSB546A-DCI is in GPIO mode. These same options are also available in I2C mode by updating registers DP0EQ_SEL, DP1EQ_SEL, DP2EQ_SEL, DP3EQ_SEL, EQ1_SEL, EQ2_SEL, and SSEQ_SEL.
| Equalization Setting # | USB3.1 DOWNSTREAM FACING PORTS | USB 3.1 UPSTREAM FACING PORT | ALL DISPLAYPORT LANES | ||||||
|---|---|---|---|---|---|---|---|---|---|
| EQ1 PIN LEVEL | EQ0 PIN LEVEL | EQ GAIN at 2.5 GHz (dB) | SSEQ1 PIN LEVEL | SSEQ0 PIN LEVEL | EQ GAIN at 2.5 GHz (dB) | DPEQ1 PIN LEVEL | DPEQ0 PIN LEVEL | EQ GAIN at 4.05 GHz (dB) | |
| 0 | 0 | 0 | 0.2 | 0 | 0 | -1.6 | 0 | 0 | 1.0 |
| 1 | 0 | R | 1.2 | 0 | R | -0.5 | 0 | R | 3.3 |
| 2 | 0 | F | 2.2 | 0 | F | 0.5 | 0 | F | 4.9 |
| 3 | 0 | 1 | 3.3 | 0 | 1 | 1.6 | 0 | 1 | 6.5 |
| 4 | R | 0 | 4.2 | R | 0 | 2.4 | R | 0 | 7.5 |
| 5 | R | R | 5.1 | R | R | 3.4 | R | R | 8.6 |
| 6 | R | F | 5.9 | R | F | 4.1 | R | F | 9.5 |
| 7 | R | 1 | 6.7 | R | 1 | 4.9 | R | 1 | 10.4 |
| 8 | F | 0 | 7.4 | F | 0 | 5.7 | F | 0 | 11.1 |
| 9 | F | R | 8.1 | F | R | 6.4 | F | R | 11.7 |
| 10 | F | F | 8.7 | F | F | 6.9 | F | F | 12.3 |
| 11 | F | 1 | 9.3 | F | 1 | 7.5 | F | 1 | 12.8 |
| 12 | 1 | 0 | 9.7 | 1 | 0 | 8.0 | 1 | 0 | 13.2 |
| 13 | 1 | R | 10.2 | 1 | R | 8.5 | 1 | R | 13.6 |
| 14 | 1 | F | 10.6 | 1 | F | 8.9 | 1 | F | 14.0 |
| 15 | 1 | 1 | 11.1 | 1 | 1 | 9.4 | 1 | 1 | 14.4 |