ZHCSGZ9G October   2017  – November 2022 TUSB564

PRODUCTION DATA  

  1. 1 特性
  2. 2 应用
  3. 3 说明
  4. 4 Revision History
  5. 5 Pin Configuration and Functions
  6. 6 Specifications
    1. 6.1 Absolute Maximum Ratings
    2. 6.2 ESD Ratings
    3. 6.3 Recommended Operating Conditions
    4. 6.4 Thermal Information
    5. 6.5 Electrical Characteristics
    6. 6.6 Switching Characteristics
    7. 6.7 Timing Requirements
    8. 6.8 Typical Characteristics
  7. 7 Parameter Measurement Information
  8. 8 Detailed Description
    1. 8.1 Overview
    2. 8.2 Functional Block Diagram
    3. 8.3 Feature Description
      1. 8.3.1 USB 3.1
      2. 8.3.2 DisplayPort
      3. 8.3.3 4-Level Inputs
      4. 8.3.4 Receiver Linear Equalization
    4. 8.4 Device Functional Modes
      1. 8.4.1 Device Configuration in GPIO Mode
      2. 8.4.2 Device Configuration In I2C Mode
      3. 8.4.3 DisplayPort Mode
      4. 8.4.4 Linear EQ Configuration
      5. 8.4.5 USB3.1 Modes
      6. 8.4.6 Operation Timing – Power Up
    5. 8.5 Programming
    6. 8.6 Register Maps
      1. 8.6.1 General Register (address = 0x0A) [reset = 00000001]
      2. 8.6.2 DisplayPort Control/Status Registers (address = 0x10) [reset = 00000000]
      3. 8.6.3 DisplayPort Control/Status Registers (address = 0x11) [reset = 00000000]
      4. 8.6.4 DisplayPort Control/Status Registers (address = 0x12) [reset = 00000000]
      5. 8.6.5 DisplayPort Control/Status Registers (address = 0x13) [reset = 00000000]
      6. 8.6.6 USB3.1 Control/Status Registers (address = 0x20) [reset = 00000000]
      7. 8.6.7 USB3.1 Control/Status Registers (address = 0x21) [reset = 00000000]
      8. 8.6.8 USB3.1 Control/Status Registers (address = 0x22) [reset = 00000000]
  9. 9 Application and Implementation
    1. 9.1 Application Information
    2. 9.2 Typical Application
      1. 9.2.1 Design Requirements
      2. 9.2.2 Detailed Design Procedure
      3. 9.2.3 Support for DisplayPort UFP_D Pin Assignment E
      4. 9.2.4 PCB Insertion Loss Curves
    3. 9.3 System Examples
      1. 9.3.1 USB 3.1 Only
      2. 9.3.2 USB 3.1 and 2 Lanes of DisplayPort
      3. 9.3.3 DisplayPort Only
  10. 10Power Supply Recommendations
  11. 11Layout
    1. 11.1 Layout Guidelines
    2. 11.2 Layout Example
  12. 12Device and Documentation Support
    1. 12.1 接收文档更新通知
    2. 12.2 支持资源
    3. 12.3 Trademarks
    4. 12.4 Electrostatic Discharge Caution
    5. 12.5 术语表
  13. 13Mechanical, Packaging, and Orderable Information

封装选项

请参考 PDF 数据表获取器件具体的封装图。

机械数据 (封装 | 引脚)
  • RNQ|40
散热焊盘机械数据 (封装 | 引脚)
订购信息

6.6 Switching Characteristics

over operating free-air temperature range (unless otherwise noted)
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
AUXp/n and SBU1/2
TAUX_PD Switch propagation delay 1400 ps
TAUX_SW_OFF Switching time CTL1 to switch OFF. Not including TCTL1_DEBOUNCE. 7500 ns
TAUX_SW_ON Switching time CTL1 to switch ON 3000 ns
TAUX_INTRA Intra-pair output skew 400 ps
USB3.1 and DisplayPort mode transition requirement (GPIO mode)
TGP_USB_4DP Min overlap of CTL0 and CTL1 when transitioning from USB 3.1 only mode to 4-Lane DisplayPort mode or vice versa 4 µs
TCTL1_DEBOUNCE CTL1 and HPDIN debounce time when transitioning from H to L 3 10 ms
I2C (SDA and SCL)
fSCL I2C clock frequency 1 MHz
tBUF Bus free time between START and STOP conditions 0.5 µs
tHDSTA Hold time after repeated START condition. After this period, the first clock pulse is generated 0.26 µs
tLOW Low period of the I2C clock 0.5 µs
tHIGH High period of the I2C clock 0.26 µs
tSUSTA Setup time for a repeated START condition 0.26 µs
tHDDAT Data hold time 0 µs
tSUDAT Data setup time 50 ns
tR Rise time of both SDA and SCL signals 120 ns
tF Fall time of both SDA and SCL signals 20 × (VI2C/5.5 V) 120 ns
tSUSTO Setup time for STOP condition 0.26 µs
Cb Capacitive load for each bus line 100 pF
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