ZHCSGZ9G October   2017  – November 2022 TUSB564

PRODUCTION DATA  

  1. 1 特性
  2. 2 应用
  3. 3 说明
  4. 4 Revision History
  5. 5 Pin Configuration and Functions
  6. 6 Specifications
    1. 6.1 Absolute Maximum Ratings
    2. 6.2 ESD Ratings
    3. 6.3 Recommended Operating Conditions
    4. 6.4 Thermal Information
    5. 6.5 Electrical Characteristics
    6. 6.6 Switching Characteristics
    7. 6.7 Timing Requirements
    8. 6.8 Typical Characteristics
  7. 7 Parameter Measurement Information
  8. 8 Detailed Description
    1. 8.1 Overview
    2. 8.2 Functional Block Diagram
    3. 8.3 Feature Description
      1. 8.3.1 USB 3.1
      2. 8.3.2 DisplayPort
      3. 8.3.3 4-Level Inputs
      4. 8.3.4 Receiver Linear Equalization
    4. 8.4 Device Functional Modes
      1. 8.4.1 Device Configuration in GPIO Mode
      2. 8.4.2 Device Configuration In I2C Mode
      3. 8.4.3 DisplayPort Mode
      4. 8.4.4 Linear EQ Configuration
      5. 8.4.5 USB3.1 Modes
      6. 8.4.6 Operation Timing – Power Up
    5. 8.5 Programming
    6. 8.6 Register Maps
      1. 8.6.1 General Register (address = 0x0A) [reset = 00000001]
      2. 8.6.2 DisplayPort Control/Status Registers (address = 0x10) [reset = 00000000]
      3. 8.6.3 DisplayPort Control/Status Registers (address = 0x11) [reset = 00000000]
      4. 8.6.4 DisplayPort Control/Status Registers (address = 0x12) [reset = 00000000]
      5. 8.6.5 DisplayPort Control/Status Registers (address = 0x13) [reset = 00000000]
      6. 8.6.6 USB3.1 Control/Status Registers (address = 0x20) [reset = 00000000]
      7. 8.6.7 USB3.1 Control/Status Registers (address = 0x21) [reset = 00000000]
      8. 8.6.8 USB3.1 Control/Status Registers (address = 0x22) [reset = 00000000]
  9. 9 Application and Implementation
    1. 9.1 Application Information
    2. 9.2 Typical Application
      1. 9.2.1 Design Requirements
      2. 9.2.2 Detailed Design Procedure
      3. 9.2.3 Support for DisplayPort UFP_D Pin Assignment E
      4. 9.2.4 PCB Insertion Loss Curves
    3. 9.3 System Examples
      1. 9.3.1 USB 3.1 Only
      2. 9.3.2 USB 3.1 and 2 Lanes of DisplayPort
      3. 9.3.3 DisplayPort Only
  10. 10Power Supply Recommendations
  11. 11Layout
    1. 11.1 Layout Guidelines
    2. 11.2 Layout Example
  12. 12Device and Documentation Support
    1. 12.1 接收文档更新通知
    2. 12.2 支持资源
    3. 12.3 Trademarks
    4. 12.4 Electrostatic Discharge Caution
    5. 12.5 术语表
  13. 13Mechanical, Packaging, and Orderable Information

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8.4.1 Device Configuration in GPIO Mode

The TUSB564 is in GPIO configuration when I2C_EN = “0”. The TUSB564 supports the following configurations: USB 3.1 only, 2 DisplayPort lanes + USB 3.1, or 4 DisplayPort lanes (no USB 3.1). The CTL1 pin controls whether DisplayPort is enabled. The combination of CTL1 and CTL0 selects between USB 3.1 only, 2 lanes of DisplayPort, or 4-lanes of DisplayPort as detailed in Table 8-2. The AUXp or AUXn to SBU1 or SBU2 mapping is controlled based on Table 8-3.

After power-up (VCC from 0 V to 3.3 V), the TUSB564 defaults to USB3.1 mode. The USB PD controller upon detecting no device attached to Type-C port or USB3.1 operation not required by attached device must take TUSB564 out of USB3.1 mode by transitioning the CTL0 pin from L to H and back to L.

Table 8-2 GPIO Configuration Control
CTL1 PIN CTL0 PIN FLIP PIN CONFIGURATION VESA DisplayPort ALT MODE
UFP_D CONFIGURATION
L L L Power Down —
L L H Power Down —
L H L One Port USB 3.1 - No Flip —
L H H One Port USB 3.1 – With Flip —
H L L 4 Lane DP - No Flip C
H L H 4 Lane DP – With Flip C
H H L One Port USB 3.1 + 2 Lane DP- No Flip D
H H H One Port USB 3.1 + 2 Lane DP– With Flip D
Table 8-3 GPIO AUXp or AUXn to SBU1 or SBU2 Mapping
CTL1 PIN FLIP PIN MAPPING
H L SBU1 → AUXn
SBU2 → AUXp
H H SBU2 → AUXn
SBU1 → AUXp
L > 2 ms X Open

Table 8-4 details the TUSB564 mux routing. This table is valid for both I2C and GPIO configuration modes.

Table 8-4 INPUT to OUTPUT Mapping
CTL1 PIN CTL0 PIN FLIP PIN FROM TO
INPUT PIN OUTPUT PIN
L L L NA NA
L L H NA NA
L H L RX1p SSRXp
RX1n SSRXn
SSTXp TX1p
SSTXn TX1n
L H H RX2p SSRXp
RX2n SSRXn
SSTXp TX2p
SSTXn TX2n
H L L TX2p DP0p
TX2n DP0n
RX2p DP1p
RX2n DP1n
RX1p DP2p
RX1n DP2n
TX1p DP3p
TX1n DP3n
H L H TX1p DP0p
TX1n DP0n
RX1p DP1p
RX1n DP1n
RX2p DP2p
RX2n DP2n
TX2p DP3p
TX2n DP3n
H H L RX1p SSRXp
RX1n SSRXn
SSTXp TX1p
SSTXn TX1n
TX2p DP0p
TX2n DP0n
RX2p DP1p
RX2n DP1n
H H H RX2p SSRXp
RX2n SSRXn
SSTXp TX2p
SSTXn TX2n
TX1p DP0p
TX1n DP0n
RX1p DP1p
RX1n DP1n
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