ZHCSGZ9G October 2017 – November 2022 TUSB564
PRODUCTION DATA
Each of the TUSB564 receiver lanes has individual controls for receiver equalization. The receiver equalization gain value can be controlled either through I2C registers or through GPIOs. Table 8-7 details the gain value for each available combination when TUSB564 is in GPIO mode. These same options are also available in I2C mode by updating registers DP0EQ_SEL, DP1EQ_SEL, DP2EQ_SEL, DP3EQ_SEL, EQ1_SEL, EQ2_SEL, and SSEQ_SEL. Each of the 4-bit EQ configuration registers is mapped to the configuration pins as follows: x_SEL = {x1[1:0],x0[1:0]} where xn[1:0] are the EQ configuration pins with pin levels mapped to 2-bit values as: 0 = 00, R = 01, F = 10, 1 = 11.
| Equalization Setting # | USB3.1 UPSTREAM FACING PORTS | USB 3.1 DOWNSTREAM FACING PORT | ALL DISPLAYPORT LANES | ||||||
|---|---|---|---|---|---|---|---|---|---|
| EQ1 PIN LEVEL | EQ0 PIN LEVEL | EQ GAIN at 2.5 GHz (dB) | SSEQ1 PIN LEVEL | SSEQ0 PIN LEVEL | EQ GAIN at 2.5 GHz (dB) | DPEQ1 PIN LEVEL | DPEQ0 PIN LEVEL | EQ GAIN at 4.05 GHz (dB) | |
| 0 | 0 | 0 | -0.9 | 0 | 0 | -2.4 | 0 | 0 | -0.3 |
| 1 | 0 | R | 0.2 | 0 | R | -1.3 | 0 | R | 1.6 |
| 2 | 0 | F | 1.2 | 0 | F | -0.4 | 0 | F | 3.0 |
| 3 | 0 | 1 | 2.2 | 0 | 1 | 0.7 | 0 | 1 | 4.4 |
| 4 | R | 0 | 3.1 | R | 0 | 1.5 | R | 0 | 5.4 |
| 5 | R | R | 4.0 | R | R | 2.5 | R | R | 6.5 |
| 6 | R | F | 4.8 | R | F | 3.2 | R | F | 7.3 |
| 7 | R | 1 | 5.6 | R | 1 | 4.0 | R | 1 | 8.1 |
| 8 | F | 0 | 6.3 | F | 0 | 4.8 | F | 0 | 8.9 |
| 9 | F | R | 7.0 | F | R | 5.5 | F | R | 9.5 |
| 10 | F | F | 7.5 | F | F | 6.0 | F | F | 10.0 |
| 11 | F | 1 | 8.1 | F | 1 | 6.6 | F | 1 | 10.6 |
| 12 | 1 | 0 | 8.5 | 1 | 0 | 7.1 | 1 | 0 | 11.0 |
| 13 | 1 | R | 9.1 | 1 | R | 7.6 | 1 | R | 11.4 |
| 14 | 1 | F | 9.5 | 1 | F | 8.0 | 1 | F | 11.8 |
| 15 | 1 | 1 | 9.9 | 1 | 1 | 8.5 | 1 | 1 | 12.1 |