ZHCS103Q March 2011 – March 2024 TUSB7320 , TUSB7340
PRODUCTION DATA
A serial EEPROM interface is implemented to pre-load several registers. The registers and corresponding bits that are loaded through the EEPROM are provided in Table 6-4.
| SERIAL EEPROM WORD ADDRESS | BYTE DESCRIPTION |
|---|---|
| 00h | TUSB73X0 Function Indicator (00h) |
| 01h | Number of Bytes (19h) |
| 02h | PCI D0h, Subsystem Vendor ID, Byte 0 |
| 03h | PCI D1h, Subsystem Vendor ID, Byte 1 |
| 04h | PCI D2h, Subsystem ID, Byte 0 |
| 05h | PCI D3h, Subsystem ID, Byte 1 |
| 06h | PCI D4h, General Control 0, Byte 0 |
| 07h | PCI D5h, General Control 0, Byte 1 |
| 08h | PCI D8h, General Control 1, Byte 0 |
| 09h | PCI DCh, General Control 2, Byte 0 |
| 0Ah | PCI E0h, USB Control, Byte 0 |
| 0Bh | PCI E1h, USB Control, Byte 1 |
| 0Ch | PCI E2h, USB Control, Byte 2 |
| 0Dh | PCI E3h, USB Control, Byte 3 |
| 0Eh | PCI E4h, De-emphasis and Swing Control, Byte 0 |
| 0Fh | PCI E5h, De-emphasis and Swing Control, Byte 1 |
| 10h | PCI E6h, De-emphasis and Swing Control, Byte 2 |
| 11h | PCI E7h, De-emphasis and Swing Control, Byte 3 |
| 12h | PCI E8h, Equalizer Control, Byte 0 |
| 13h | PCI E9h, Equalizer Control, Byte 1 |
| 14h | PCI EAh, Equalizer Control, Byte 2 |
| 15h | PCI EBh, Equalizer Control, Byte 3 |
| 16h | PCI ECh, Custom PHY Transmit/Receive Control, Byte 0 |
| 17h | PCI EDh, Custom PHY Transmit/Receive Control, Byte 1 |
| 18h | PCI EEh, Custom PHY Transmit/Receive Control, Byte 2 |
| 19h | PCI EFh, Custom PHY Transmit/Receive Control, Byte 3 |
| 1Ah | PCI 61h, Frame Length Adjustment Register |
| 1Bh | End of List Indicator (80h) |
This format must be explicitly followed for the host controller to correctly load initialization values from a serial EEPROM. All byte locations must be considered when programming the EEPROM.
The serial EEPROM is addressed by the host controller at target address 1010 000b. This target address is internally hardwired and cannot be changed by the system designer. Therefore, all three hardware address bits for the EEPROM are tied to VSS to achieve this address. The serial EEPROM in the sample application circuit (Figure 6-2) assumes the 1010b high-address nibble. The lower three address bits are terminal inputs to the chip, and the sample application shows these terminal inputs tied to VSS.
During an EEPROM download operation, bit 4 (ROMBUSY) in the serial-bus control and status register is asserted. After the download is finished, bit 0 (ROM_ERR) in the serial-bus control and status register may be monitored to verify a successful download.