When using an external clock source, the reference clock should have a ±100 PPM or better frequency stability and have less than 50-ps absolute peak to peak jitter or less than 25-ps peak to peak jitter after applying the USB 3.0 jitter transfer function. XI should be tied to the clock source and XO should be left floating. The input clock must be 1.8-V LVCMOS; this input is not 3.3-V tolerant.