1. Assert PERST# to the device.
2. Apply 3.3-V followed by 1.1-V voltages. The recommended 1.1-V and 3.3-V power supply ramp time is greater than or equal to 1 ms (measured from 0% to 100%).
3. GRST# must remain asserted until both the 1.1-V and 3.3-V voltages have reached the minimum recommended operating voltage, see Recommended Operating Conditions. If a 24 MHz or 48 MHz reference clock is used instead of a crystal, GRST# must remain asserted until the 24 MHz or 48 MHz clock is stable.
4. Apply a stable PCI Express reference clock.
5. To meet PCI Express specification requirements, PERST cannot be deasserted until the following two delay requirements are satisfied:

Wait a minimum of 100 µs after applying a stable PCI Express reference clock. The 100-µs limit satisfies the requirement for stable device clocks by the de-assertion of PERST.

Wait a minimum of 100 ms after applying power. The 100-ms limit satisfies the requirement for stable power by the de-assertion of PERST.

See the power-up sequencing diagram in Figure 7-16.

Figure 7-16 Power-Up Sequence