ZHCS103Q March 2011 – March 2024 TUSB7320 , TUSB7340
PRODUCTION DATA
The host controller contains both 1.1-V and 3.3-V power terminals. The following power-up and power-down sequences describe how power is applied to these terminals.
In addition, the host controller has three resets: PERST#, GRST#, and an internal power-on-reset. These resets are fully described in the next section. The following power-up and power-down sequences describe how PERST# is applied to the host controller.
The application of the PCI Express reference clock (PCIE_REFCLK) is important to the power-up/-down sequence and is included in the following power-up and power-down descriptions.