ZHCSDC7C July   2014  – June 2017 TUSB8020B

PRODUCTION DATA.  

  1. 1 特性
  2. 2 应用
  3. 3 说明
  4. 4 修订历史记录
  5. 5 说明 （续）
  6. 6 Pin Configuration and Functions
  7. 7 Specifications
    1. 7.1 Absolute Maximum Ratings
    2. 7.2 ESD Ratings
    3. 7.3 Recommended Operating Conditions
    4. 7.4 Thermal Information
    5. 7.5 3.3-V I/O Electrical Characteristics
    6. 7.6 Power-Up Timing Requirements
    7. 7.7 Hub Input Supply Current
  8. 8 Detailed Description
    1. 8.1 Overview
    2. 8.2 Functional Block Diagram
    3. 8.3 Feature Description
      1. 8.3.1 Battery Charging Features
      2. 8.3.2 USB Power Management
      3. 8.3.3 One-Time Programmable (OTP) Configuration
      4. 8.3.4 Clock Generation
        1. 8.3.4.1 Crystal Requirements
        2. 8.3.4.2 Input Clock Requirements
      5. 8.3.5 Power-Up and Reset
    4. 8.4 Device Functional Modes
      1. 8.4.1 External Configuration Interface
      2. 8.4.2 I2C EEPROM Operation
      3. 8.4.3 SMBus Slave Operation
    5. 8.5 Register Maps
      1. 8.5.1 Configuration Registers
        1. 8.5.1.1  ROM Signature Register (offset = 0h) [reset = 0h]
        2. 8.5.1.2  Vendor ID LSB Register (offset = 1h) [reset = 51h]
        3. 8.5.1.3  Vendor ID MSB Register (offset = 2h) [reset = 4h]
        4. 8.5.1.4  Product ID LSB Register (offset = 3h) [reset = 25h]
        5. 8.5.1.5  Product ID MSB Register (offset = 4h) [reset = 80h]
        6. 8.5.1.6  Device Configuration Register (offset = 5h) [reset = 1Xh]
        7. 8.5.1.7  Battery Charging Support Register (offset = 6h) [reset = 0Xh]
        8. 8.5.1.8  Device Removable Configuration Register (offset = 7h) [reset = 0Xh]
        9. 8.5.1.9  Port Used Configuration Register (offset = 8h) [reset = 0h]
        10. 8.5.1.10 PHY Custom Configuration Register (offset = 9h) [reset = 0h]
        11. 8.5.1.11 Device Configuration Register 2 (offset = Ah)
        12. 8.5.1.12 UUID Registers (offset = 10h to 1Fh)
        13. 8.5.1.13 Language ID LSB Register (offset = 20h)
        14. 8.5.1.14 Language ID MSB Register (offset = 21h)
        15. 8.5.1.15 Serial Number String Length Register (offset = 22h)
        16. 8.5.1.16 Manufacturer String Length Register (offset = 23h)
        17. 8.5.1.17 Product String Length Register (offset = 24h)
        18. 8.5.1.18 Serial Number Registers (offset = 30h to 4Fh)
        19. 8.5.1.19 Manufacturer String Registers (offset = 50h to 8Fh)
        20. 8.5.1.20 Product String Registers (offset = 90h to CFh)
        21. 8.5.1.21 Additional Feature Configuration Register (offset = F0h)
        22. 8.5.1.22 Charging Port Control Register (offset = F2h)
        23. 8.5.1.23 Device Status and Command Register (offset = F8h)
  9. 9 Application and Implementation
    1. 9.1 Application Information
    2. 9.2 Typical Application
      1. 9.2.1 Design Requirements
      2. 9.2.2 Detailed Design Procedure
        1. 9.2.2.1 Upstream Port Implementation
        2. 9.2.2.2 Downstream Port 1 Implementation
        3. 9.2.2.3 Downstream Port 2 Implementation
        4. 9.2.2.4 VBUS Power Switch Implementation
        5. 9.2.2.5 Clock, Reset, and Miscellaneous
        6. 9.2.2.6 Power Implementation
      3. 9.2.3 Application Curves
  10. 10Power Supply Recommendations
    1. 10.1 Power Supply
    2. 10.2 Downstream Port Power
    3. 10.3 Ground
  11. 11Layout
    1. 11.1 Layout Guidelines
      1. 11.1.1 Placement
      2. 11.1.2 Package Specific
      3. 11.1.3 Differential Pairs
    2. 11.2 Layout Example
      1. 11.2.1 Upstream Port
      2. 11.2.2 Downstream Port
      3. 11.2.3 Thermal Pad
  12. 12器件和文档支持
    1. 12.1 社区资源
    2. 12.2 商标
    3. 12.3 静电放电警告
    4. 12.4 Glossary
  13. 13机械、封装和可订购信息

封装选项

机械数据 (封装 | 引脚)
散热焊盘机械数据 (封装 | 引脚)
订购信息

11 Layout

11.1 Layout Guidelines

11.1.1 Placement

  1. A 9.53-kΩ ±1% resistor connected to terminal USB_R1 should be placed as close as possible to the TUSB8020B.
  2. A 0.1-µF capacitor should be placed as close as possible on each VDD and VDD33 power pin.
  3. The 100-nF capacitors on the SSTXP and SSTXM nets should be placed close to the USB connector (type A, type B, and so forth).
  4. The ESD and EMI protection devices (if used) should also be placed as possible to the USB connector.
  5. If a crystal is used, it must be placed as close as possible to the TUSB8020B device’s XI and XO terminals.
  6. Place voltage regulators as far away as possible from the TUSB8020B, crystal, and differential pairs.
  7. In general, the large bulk capacitors associated with each power rail should be placed as close as possible to the voltage regulators.

11.1.2 Package Specific

  1. The TUSB8020B package has a 0.5-mm pin pitch.
  2. The TUSB8020B package has a 3.6-mm × 3.6-mm thermal pad. This thermal pad must be connected to ground through a system of vias.
  3. All vias under device, except for those connected to thermal pad, should be solder masked to avoid potential issues with thermal pad layouts.

11.1.3 Differential Pairs

This section describes the layout recommendations for all of the TUSB8020B differential pairs: USB_DP_XX, USB_DM_XX, USB_SSTXP_XX, USB_SSTXM_XX, USB_SSRXP_XX, and USB_SSRXM_XX.

  • Must be designed with a differential impedance of 90 Ω ±10%.
  • To minimize crosstalk, TI recommends to keep high-speed signals away from each other. Each pair should be separated by at least 5× the signal trace width. Separating with ground as depicted in the layout example also helps minimize crosstalk.
  • Route all differential pairs on the same layer adjacent to a solid ground plane.
  • Do not route differential pairs over any plane split.
  • Adding test points causes impedance discontinuity, and therefore, negatively impacts signal performance. If test points are used, they should be placed in series and symmetrically. They must not be placed in a manner that causes stub on the differential pair.
  • Avoid 90° turns in trace. The use of bends in differential traces should be kept to a minimum. When bends are used, the number of left and right bends should be as equal as possible and the angle of the bend should be ≥135°. Taking this action minimizes any length mismatch caused by the bends, and therefore, minimizes the impact bends have on EMI.
  • Minimize the trace lengths of the differential pair traces. Eight inches is the maximum recommended trace length for SS differential-pair signals and USB 2.0 differential-pair signals. Longer trace lengths require very careful routing to assure proper signal integrity.
  • Match the etch lengths of the differential pair traces (that is DP and DM or SSRXP and SSRXM or SSTXP and SSTXM). There should be less than 5-mils difference between a SS differential-pair signal and its complement. The USB 2.0 differential pairs should not exceed 50-mils relative trace length difference.
  • The etch lengths of the differential pair groups do not need to match (that is the length of the SSRX pair to that of the SSTX pair), but all trace lengths should be minimized.
  • Minimize the use of vias in the differential-pair paths as much as possible. If this is not practical, ensure that the same via type and placement are used for both signals in a pair. Any vias used should be placed as close as possible to the TUSB8020B device.
  • To ease routing, the polarity of the SS differential pairs can be swapped. This means that SSTXP can be routed to SSTXM or SSRXM can be routed to SSRXP.
  • Do not place power fuses across the differential-pair traces.

11.2 Layout Example

11.2.1 Upstream Port

TUSB8020B routing_upstream_port_sllsef7.gif

11.2.2 Downstream Port

TUSB8020B routing_downstream_port_sllsef7.gif

11.2.3 Thermal Pad

TUSB8020B thermal_pad_layout_sllsef7.gif
千亿体育app官网登录(中国)官方网站IOS/安卓通用版/手机APP | 米乐app下载官网（中国）|ios|Android/通用版APP最新版 | 米乐|米乐·M6（中国大陆）官方网站 | 千亿体育登陆地址 | 华体会体育（中国）HTH·官方网站 | 千赢qy国际_全站最新版千赢qy国际V6.2.14安卓/IOS下载 | 18新利网v1.2.5|中国官方网站 | bob电竞真人（中国官网）安卓/ios苹果/电脑版【1.97.95版下载】 | 千亿体育app官方下载(中国)官方网站IOS/安卓/手机APP下载安装 |