ZHCSDC7C July   2014  – June 2017 TUSB8020B

PRODUCTION DATA.  

  1. 1 特性
  2. 2 应用
  3. 3 说明
  4. 4 修订历史记录
  5. 5 说明 （续）
  6. 6 Pin Configuration and Functions
  7. 7 Specifications
    1. 7.1 Absolute Maximum Ratings
    2. 7.2 ESD Ratings
    3. 7.3 Recommended Operating Conditions
    4. 7.4 Thermal Information
    5. 7.5 3.3-V I/O Electrical Characteristics
    6. 7.6 Power-Up Timing Requirements
    7. 7.7 Hub Input Supply Current
  8. 8 Detailed Description
    1. 8.1 Overview
    2. 8.2 Functional Block Diagram
    3. 8.3 Feature Description
      1. 8.3.1 Battery Charging Features
      2. 8.3.2 USB Power Management
      3. 8.3.3 One-Time Programmable (OTP) Configuration
      4. 8.3.4 Clock Generation
        1. 8.3.4.1 Crystal Requirements
        2. 8.3.4.2 Input Clock Requirements
      5. 8.3.5 Power-Up and Reset
    4. 8.4 Device Functional Modes
      1. 8.4.1 External Configuration Interface
      2. 8.4.2 I2C EEPROM Operation
      3. 8.4.3 SMBus Slave Operation
    5. 8.5 Register Maps
      1. 8.5.1 Configuration Registers
        1. 8.5.1.1  ROM Signature Register (offset = 0h) [reset = 0h]
        2. 8.5.1.2  Vendor ID LSB Register (offset = 1h) [reset = 51h]
        3. 8.5.1.3  Vendor ID MSB Register (offset = 2h) [reset = 4h]
        4. 8.5.1.4  Product ID LSB Register (offset = 3h) [reset = 25h]
        5. 8.5.1.5  Product ID MSB Register (offset = 4h) [reset = 80h]
        6. 8.5.1.6  Device Configuration Register (offset = 5h) [reset = 1Xh]
        7. 8.5.1.7  Battery Charging Support Register (offset = 6h) [reset = 0Xh]
        8. 8.5.1.8  Device Removable Configuration Register (offset = 7h) [reset = 0Xh]
        9. 8.5.1.9  Port Used Configuration Register (offset = 8h) [reset = 0h]
        10. 8.5.1.10 PHY Custom Configuration Register (offset = 9h) [reset = 0h]
        11. 8.5.1.11 Device Configuration Register 2 (offset = Ah)
        12. 8.5.1.12 UUID Registers (offset = 10h to 1Fh)
        13. 8.5.1.13 Language ID LSB Register (offset = 20h)
        14. 8.5.1.14 Language ID MSB Register (offset = 21h)
        15. 8.5.1.15 Serial Number String Length Register (offset = 22h)
        16. 8.5.1.16 Manufacturer String Length Register (offset = 23h)
        17. 8.5.1.17 Product String Length Register (offset = 24h)
        18. 8.5.1.18 Serial Number Registers (offset = 30h to 4Fh)
        19. 8.5.1.19 Manufacturer String Registers (offset = 50h to 8Fh)
        20. 8.5.1.20 Product String Registers (offset = 90h to CFh)
        21. 8.5.1.21 Additional Feature Configuration Register (offset = F0h)
        22. 8.5.1.22 Charging Port Control Register (offset = F2h)
        23. 8.5.1.23 Device Status and Command Register (offset = F8h)
  9. 9 Application and Implementation
    1. 9.1 Application Information
    2. 9.2 Typical Application
      1. 9.2.1 Design Requirements
      2. 9.2.2 Detailed Design Procedure
        1. 9.2.2.1 Upstream Port Implementation
        2. 9.2.2.2 Downstream Port 1 Implementation
        3. 9.2.2.3 Downstream Port 2 Implementation
        4. 9.2.2.4 VBUS Power Switch Implementation
        5. 9.2.2.5 Clock, Reset, and Miscellaneous
        6. 9.2.2.6 Power Implementation
      3. 9.2.3 Application Curves
  10. 10Power Supply Recommendations
    1. 10.1 Power Supply
    2. 10.2 Downstream Port Power
    3. 10.3 Ground
  11. 11Layout
    1. 11.1 Layout Guidelines
      1. 11.1.1 Placement
      2. 11.1.2 Package Specific
      3. 11.1.3 Differential Pairs
    2. 11.2 Layout Example
      1. 11.2.1 Upstream Port
      2. 11.2.2 Downstream Port
      3. 11.2.3 Thermal Pad
  12. 12器件和文档支持
    1. 12.1 社区资源
    2. 12.2 商标
    3. 12.3 静电放电警告
    4. 12.4 Glossary
  13. 13机械、封装和可订购信息

封装选项

机械数据 (封装 | 引脚)
散热焊盘机械数据 (封装 | 引脚)
订购信息

6 Pin Configuration and Functions

PHP Package
36 Pin (HTQFP)
(Top View)
TUSB8020B po_llsef6.gif

Pin Functions

PIN TYPE DESCRIPTION
NAME NO.
CLOCK AND RESET SIGNALS
GRSTz 11 I
PU		 Global power reset. This reset brings all of the TUSB8020B internal registers to their default states. When GRSTz is asserted, the device is completely nonfunctional.
XI 38 I Crystal input. This terminal is the crystal input for the internal oscillator. The input may alternately be driven by the output of an external oscillator. When using a crystal a 1-MΩ feedback resistor is required between XI and XO.
XO 39 O Crystal output. This terminal is the crystal output for the internal oscillator. If XI is driven by an external oscillator this pin may be left unconnected. When using a crystal a 1-MΩ feedback resistor is required between XI and XO.
USB UPSTREAM SIGNALS
USB_SSTXP_UP 29 O USB SuperSpeed transmitter differential pair (positive)
USB_SSTXM_UP 28 O USB SuperSpeed transmitter differential pair (negative)
USB_SSRXP_UP 32 I USB SuperSpeed receiver differential pair (positive)
USB_SSRXM_UP 31 I USB SuperSpeed receiver differential pair (negative)
USB_DP_UP 26 I/O USB high-speed differential transceiver (positive)
USB_DM_UP 27 I/O USB high-speed differential transceiver (negative)
USB_R1 24 I Precision resistor reference. A 9.53-kΩ ±1% resistor should be connected between USB_R1 and GND.
USB_VBUS 9 I USB upstream port power monitor. The VBUS detection requires a voltage divider. The signal USB_VBUS must be connected to VBUS through a 90.9-kΩ ±1% resistor, and to ground through a
10-kΩ ±1% resistor from the signal to ground.
USB DOWNSTREAM SIGNALS
USB_SSTXP_DN1 43 O USB SuperSpeed transmitter differential pair (positive) downstream port 1.
USB_SSTXM_DN1 44 O USB SuperSpeed transmitter differential pair (negative) downstream port 1.
USB_SSRXP_DN1 46 I USB SuperSpeed receiver differential pair (positive) downstream port 1.
USB_SSRXM_DN1 47 I USB SuperSpeed receiver differential pair (negative) downstream port 1.
USB_DP_DN1 41 I/O USB high-speed differential transceiver (positive) downstream port 1.
USB_DM_DN1 42 I/O USB high-speed differential transceiver (negative) downstream port 1.
PWRCTL1/BATEN1 4 I/O
PD		 USB port 1 power-on control for downstream power or battery charging enable. The terminal is used for control of the downstream power switch for Port 1.
In addition, the value of the terminal is sampled at the deassertion of reset to determine the value of the battery charging support for Port 1 as indicated in the Battery Charging Support register.
0 = Battery charging not supported
1 = Battery charging supported
OVERCUR1z 5 I
PU		 USB DS port 1 overcurrent detection input. This terminal is used to connect the over current output of the downstream port power switch for port 1.
0 = An overcurrent event has occurred
1 = An overcurrent event has not occurred
If power management is enabled, the external circuitry needed should be determined by the power switch. In ganged mode, either OVERCUR1z or OVERCUR2z can be used. In ganged mode, the overcurrent will be reported as a hub event instead of a port event.
USB_SSTXP_DN2 16 O USB SuperSpeed transmitter differential pair (positive) downstream port 2.
USB_SSTXM_DN2 17 O USB SuperSpeed transmitter differential pair (negative) downstream port 2.
USB_SSRXP_DN2 19 I USB SuperSpeed receiver differential pair (positive) downstream port 2.
USB_SSRXM_DN2 20 I USB SuperSpeed receiver differential pair (negative) downstream port 2.
USB_DP_DN2 14 I/O USB high-speed differential transceiver (positive) downstream port 2.
USB_DM_DN2 15 I/O USB high-speed differential transceiver (negative) downstream port 2.
PWRCTL2/BATEN2 6 I/O
PD		 Power-on control /battery charging enable for downstream port 2. This terminal is used for control of the downstream power switch for port 2.
The value of the terminal is sampled at the deassertion of reset to determine the value of the battery charging support for port 2 as indicated in the Battery Charging Support register.
0 = Battery charging not supported
1 = Battery charging supported
OVERCUR2z 8 I
PU		 Overcurrent detection for downstream port 2. This terminal is used to connect the over current output of the downstream port power switch for port 2.
0 = An overcurrent event has occurred
1 = An overcurrent event has not occurred
If power management is enabled, the external circuitry needed should be determined by the power switch. In ganged mode either OVERCUR1z or OVERCUR2z can be used. In ganged mode the overcurrent will be reported as a hub event instead of a port event.
I2C/SMBUS SIGNALS
SCL/SMBCLK 2 I/O
PD		 I2C clock/SMBus clock. Function of terminal depends on the setting of the SMBUSz input.
When SMBUSz = 1, this terminal acts as the serial clock interface for an I2C EEPROM.
When SMBUSz = 0, this terminal acts as the serial clock interface for an SMBus host.
This pin must be pulled up to use the OTP ROM.
Can be left unconnected if external interface not implemented.
SDA/SMBDAT 3 I/O
PD		 I2C data/SMBus data. Function of terminal depends on the setting of the SMBUSz input.
When SMBUSz = 1, this terminal acts as the serial data interface for an I2C EEPROM.
When SMBUSz = 0, this terminal acts as the serial data interface for an SMBus host.
This pin must be pulled up to use the OTP ROM.
Can be left unconnected if external interface not implemented.
TEST AND MISCELLANEOUS SIGNALS
SMBUSz/SS_DN2 22 I
PU		 SMBUS mode / SuperSpeed USB Status for downstream port 2
The value of the terminal is sampled at the deassertion of reset to enable I2C or SMBus mode.
0 = SMBus mode selected
1 = I2C mode selected
After reset, this signal indicates the SuperSpeed USB connection status of downstream port 2. A value of 1 indicates the connection is SuperSpeed USB.
PWRCTL_POL/SS_DN1 21 I/O
PD		 Power control polarity / SuperSpeed USB status for downstream port 1.
The value of the terminal is sampled at the deassertion of reset to set the polarity of PWRCTL[2:1].
0 = PWRCTL polarity is active high.
1 = PWRCTL polarity is active low.
After reset, this signal indicates the SuperSpeed USB connection status of downstream port 1. A value of 1 indicates the connection is SuperSpeed USB.
GANGED/SMBA2/
HS_UP		 35 I
PU		 Ganged operation enable/SMBus address bit 2/ high-speed status for upstream port
The value of the terminal is sampled at the deassertion of reset to set the power switch and over current detection mode as follows:
0 = Individual power control supported when power switching is enabled.
1 = Power control gangs supported when power switching is enabled.
When SMBus mode is enabled using SMBUSz, this terminal sets the value of the SMBus slave address bit 2. SMBus slave address bits 2 and 3 are always 1 for the TUSB8020B.
After reset, this signal indicates the high-speed USB connection status of the upstream port. A value of 1 indicates the upstream port is connected to a high-speed USB capable port.
FULLPWRMGMTz/
SMBA1/SS_UP		 36 I, PU Full power management enable/ SMBus Address bit 1/ Super-Speed USB status for upstream port
The value of the terminal is sampled at the deassertion of reset to set the power switch control follows:
0 = Power switching supported
1 = Power switching not supported
Full power management is the ability to control power to the downstream ports of the TUSB8020B using PWRCTL[2:1]/BATEN[2:1].
When SMBus mode is enabled using SMBUSz, this terminal sets the value of the SMBus slave address bit 1. SMBus slave address bit 3 is always 1 for the TUSB8020B.
Can be left unconnected if full power management and SMBus are not implemented.
After reset, this signal indicates the SuperSpeed USB connection status of the upstream port. A value of 1 indicates the upstream port is connected to a SuperSpeed USB capable port.
TEST 10 I
PD		 TEST mode enable. When this terminal is asserted high at reset enables test mode. This terminal is reserved for factory use. It is recommended to pull-down this terminal to ground.
POWER AND GROUND SIGNALS
VDD 1, 12, 18, 30, 34, 45 PWR 1.1-V power rail
VDD33 7, 13, 23, 25, 33, 37, 40, 48 PWR 3.3-V power rail
GND PAD — Ground
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