ZHCSJZ0 June   2019 TUSB8042A

PRODUCTION DATA.  

  1. 1 特性
  2. 2 应用
  3. 3 说明
    1.     图
  4. 4 修订历史记录
  5. 5 说明 （续）
  6. 6 Pin Configuration and Functions
    1.     Pin Functions
  7. 7 Specifications
    1. 7.1 Absolute Maximum Ratings
    2. 7.2 ESD Ratings
    3. 7.3 Recommended Operating Conditions
    4. 7.4 Thermal Information
    5. 7.5 Electrical Characteristics
    6. 7.6 Timing Requirements
  8. 8 Detailed Description
    1. 8.1 Overview
    2. 8.2 Functional Block Diagram
    3. 8.3 Feature Description
      1. 8.3.1 Battery Charging Features
      2. 8.3.2 USB Power Management
      3. 8.3.3 One Time Programmable (OTP) Configuration
      4. 8.3.4 Clock Generation
      5. 8.3.5 Crystal Requirements
      6. 8.3.6 Input Clock Requirements
      7. 8.3.7 Power-Up and Reset
    4. 8.4 Device Functional Modes
      1. 8.4.1 External Configuration Interface
      2. 8.4.2 I2C EEPROM Operation
      3. 8.4.3 Port Configuration
      4. 8.4.4 SMBus Slave Operation
    5. 8.5 Register Maps
      1. 8.5.1  Configuration Registers
      2. 8.5.2  ROM Signature Register
        1. Table 6. Bit Descriptions – ROM Signature Register
      3. 8.5.3  Vendor ID LSB Register
        1. Table 7. Bit Descriptions – Vendor ID LSB Register
      4. 8.5.4  Vendor ID MSB Register
        1. Table 8. Bit Descriptions – Vendor ID MSB Register
      5. 8.5.5  Product ID LSB Register
        1. Table 9. Bit Descriptions – Product ID LSB Register
      6. 8.5.6  Product ID MSB Register
        1. Table 10. Bit Descriptions – Product ID MSB Register
      7. 8.5.7  Device Configuration Register
        1. Table 11. Bit Descriptions – Device Configuration Register
      8. 8.5.8  Battery Charging Support Register
        1. Table 12. Bit Descriptions – Battery Charging Support Register
      9. 8.5.9  Device Removable Configuration Register
        1. Table 13. Bit Descriptions – Device Removable Configuration Register
      10. 8.5.10 Port Used Configuration Register
        1. Table 14. Bit Descriptions – Port Used Configuration Register
      11. 8.5.11 Device Configuration Register 2
        1. Table 15. Bit Descriptions – Device Configuration Register 2
      12. 8.5.12 USB 2.0 Port Polarity Control Register
        1. Table 16. Bit Descriptions – USB 2.0 Port Polarity Control Register
      13. 8.5.13 UUID Registers
        1. Table 17. Bit Descriptions – UUID Byte N Register
      14. 8.5.14 Language ID LSB Register
        1. Table 18. Bit Descriptions – Language ID LSB Register
      15. 8.5.15 Language ID MSB Register
        1. Table 19. Bit Descriptions – Language ID MSB Register
      16. 8.5.16 Serial Number String Length Register
        1. Table 20. Bit Descriptions – Serial Number String Length Register
      17. 8.5.17 Manufacturer String Length Register
        1. Table 21. Bit Descriptions – Manufacturer String Length Register
      18. 8.5.18 Product String Length Register
        1. Table 22. Bit Descriptions – Product String Length Register
      19. 8.5.19 Device Configuration Register 3
        1. Table 23. Bit Descriptions – Device Configuration Register 3
      20. 8.5.20 USB 2.0 Only Port Register
        1. Table 24. Bit Descriptions – USB 2.0 Only Port Register
      21. 8.5.21 Serial Number String Registers
        1. Table 25. Bit Descriptions – Serial Number Registers
      22. 8.5.22 Manufacturer String Registers
        1. Table 26. Bit Descriptions – Manufacturer String Registers
      23. 8.5.23 Product String Registers
        1. Table 27. Bit Descriptions – Product String Byte N Register
      24. 8.5.24 Additional Feature Configuration Register
        1. Table 28. Bit Descriptions – Additional Feature Configuration Register
      25. 8.5.25 SMBus Device Status and Command Register
        1. Table 29. Bit Descriptions – SMBus Device Status and Command Register
  9. 9 Application and Implementation
    1. 9.1 Application Information
    2. 9.2 Typical Application
      1. 9.2.1 Discrete USB Hub Product
        1. 9.2.1.1 Design Requirements
        2. 9.2.1.2 Detailed Design Procedure
          1. 9.2.1.2.1 Upstream Port Implementation
          2. 9.2.1.2.2 Downstream Port 1 Implementation
          3. 9.2.1.2.3 Downstream Port 2 Implementation
          4. 9.2.1.2.4 Downstream Port 3 Implementation
          5. 9.2.1.2.5 Downstream Port 4 Implementation
          6. 9.2.1.2.6 VBUS Power Switch Implementation
          7. 9.2.1.2.7 Clock, Reset, and Misc
          8. 9.2.1.2.8 TUSB8042A Power Implementation
        3. 9.2.1.3 Application Curves
  10. 10Power Supply Recommendations
    1. 10.1 TUSB8042A Power Supply
    2. 10.2 Downstream Port Power
    3. 10.3 Ground
  11. 11Layout
    1. 11.1 Layout Guidelines
      1. 11.1.1 Placement
      2. 11.1.2 Package Specific
      3. 11.1.3 Differential Pairs
    2. 11.2 Layout Examples
      1. 11.2.1 Upstream Port
      2. 11.2.2 Downstream Port
  12. 12器件和文档支持
    1. 12.1 接收文档更新通知
    2. 12.2 社区资源
    3. 12.3 商标
    4. 12.4 静电放电警告
    5. 12.5 Glossary
  13. 13机械、封装和可订购信息

封装选项

机械数据 (封装 | 引脚)
散热焊盘机械数据 (封装 | 引脚)
订购信息

8.3.7 Power-Up and Reset

The TUSB8042A does not have specific power sequencing requirements with respect to the core power (VDD) or I/O and analog power (VDD33) as long as GRSTz is held in an asserted state while supplies ramp. The core power (VDD) or I/O power (VDD33) may be powered up for an indefinite period of time while the other is not powered up if all of these constraints are met:

  • All maximum ratings and recommended operating conditions are observed.
  • All warnings about exposure to maximum rated and recommended conditions are observed, particularly junction temperature. These apply to power transitions as well as normal operation.
  • Bus contention while VDD33 is powered up must be limited to 100 hours over the projected life-time of the device.
  • Bus contention while VDD33 is powered down may violate the absolute maximum ratings.

A supply bus is powered up when the voltage is within the recommended operating range. It is powered down when it is below that range, either stable or in transition.

A minimum reset duration of 3 ms is required. This is defined as the time when the power supplies are in the recommended operating range to the de-assertion of GRSTz. This can be generated using programmable-delay supervisory device or using an RC circuit. When a RC circuit is used, the external capacitor size chosen must be large enough to meet the 3ms minimum duration requirement. The R of the RC circuit is the internal RPU.
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