ZHCSJZ0 June 2019 TUSB8042A
PRODUCTION DATA.
| PIN | I/O | DESCRIPTION | |||||||
|---|---|---|---|---|---|---|---|---|---|
| NAME | NO. | ||||||||
| Clock and Reset Signals | |||||||||
| GRSTz | 50 | I, PU | Global power reset. This reset brings all of the TUSB8042A internal registers to their default states. When GRSTz is asserted, the device is completely nonfunctional. | ||||||
| XI | 62 | I | Crystal input. This pin is the crystal input for the internal oscillator. The input may alternately be driven by the output of an external oscillator. When using a crystal a 1-MΩ feedback resistor is required between XI and XO. | ||||||
| XO | 61 | O | Crystal output. This pin is the crystal output for the internal oscillator. If XI is driven by an external oscillator this pin may be left unconnected. When using a crystal a 1-MΩ feedback resistor is required between XI and XO. | ||||||
| USB Upstream Signals | |||||||||
| USB_SSTXP_UP | 55 | O | USB SuperSpeed transmitter differential pair (positive) | ||||||
| USB_SSTXM_UP | 56 | O | USB SuperSpeed transmitter differential pair (negative) | ||||||
| USB_SSRXP_UP | 58 | I | USB SuperSpeed receiver differential pair (positive) | ||||||
| USB_SSRXM_UP | 59 | I | USB SuperSpeed receiver differential pair (negative) | ||||||
| USB_DP_UP | 53 | I/O | USB High-speed differential transceiver (positive) | ||||||
| USB_DM_UP | 54 | I/O | USB High-speed differential transceiver (negative) | ||||||
| USB_R1 | 64 | I | Precision resistor reference. A 9.53-kΩ ±1% resistor should be connected between USB_R1 and GND. | ||||||
| USB_VBUS | 48 | I | USB upstream port power monitor. The VBUS detection requires a voltage divider. The signal USB_VBUS must be connected to VBUS through a 90.9-KΩ ±1% resistor, and to ground through a 10-kΩ ±1% resistor from the signal to ground. | ||||||
| USB Downstream Signals | |||||||||
| USB_SSTXP_DN1 | 3 | O | USB SuperSpeed transmitter differential pair (positive) | ||||||
| USB_SSTXM_DN1 | 4 | O | USB SuperSpeed transmitter differential pair (negative) | ||||||
| USB_SSRXP_DN1 | 6 | I | USB SuperSpeed receiver differential pair (positive) | ||||||
| USB_SSRXM_DN1 | 7 | I | USB SuperSpeed receiver differential pair (negative) | ||||||
| USB_DP_DN1 | 1 | I/O | USB High-speed differential transceiver (positive) | ||||||
| USB_DM_DN1 | 2 | I/O | USB High-speed differential transceiver (negative) | ||||||
| PWRCTL1/BATEN1 | 36 | I/O, PD | USB Port 1 Power On Control for Downstream Power/Battery Charging Enable. The pin is used for control of the downstream power switch for Port 1. This pin be left unconnected if power management is not implemented. | ||||||
| In addition, the value of the pin is sampled at the de-assertion of reset to determine the value of the battery charging support for Port 1 as indicated in the Battery Charging Support register: | |||||||||
| 0 = Battery charging not supported | |||||||||
| 1 = Battery charging supported | |||||||||
| OVERCUR1z | 46 | I, PU | USB Port 1 Over-Current Detection. This pin is typically connected to the over current output of the downstream port power switch for Port 1. | ||||||
| 0 = An over current event has occurred | |||||||||
| 1 = An over current event has not occurred | |||||||||
| When GANGED power management is enabled, this pin or one of the other OVERCURz pins must be connected to the over current output of the power switch or circuit which detects the over current conditions. For the case when another OVERCURz pin is used, this pin can be left unconnected. | |||||||||
| USB_SSTXP_DN2 | 11 | O | USB SuperSpeed transmitter differential pair (positive) | ||||||
| USB_SSTXM_DN2 | 12 | O | USB SuperSpeed transmitter differential pair (negative) | ||||||
| USB_SSRXP_DN2 | 14 | I | USB SuperSpeed receiver differential pair (positive) | ||||||
| USB_SSRXM_DN2 | 15 | I | USB SuperSpeed receiver differential pair (negative) | ||||||
| USB_DP_DN2 | 9 | I/O | USB High-speed differential transceiver (positive) | ||||||
| USB_DM_DN2 | 10 | I/O | USB High-speed differential transceiver (negative) | ||||||
| PWRCTL2/BATEN2 | 35 | I/O, PD | USB Port 2 Power On Control for Downstream Power/Battery Charging Enable. The pin is used for control of the downstream power switch for Port 2. This pin be left unconnected if power management is not implemented. | ||||||
| In addition, the value of the pin is sampled at the de-assertion of reset to determine the value of the battery charging support for Port 2 as indicated in the Battery Charging Support register: | |||||||||
| 0 = Battery charging not supported | |||||||||
| 1 = Battery charging supported | |||||||||
| OVERCUR2z | 47 | I, PU | USB Port 2 Over-Current Detection. This pin is typically connected to the over current output of the downstream port power switch for Port 2. | ||||||
| 0 = An over current event has occurred | |||||||||
| 1 = An over current event has not occurred | |||||||||
| When GANGED power management is enabled, this pin or one of the other OVERCURz pins must be connected to the over current output of the power switch or circuit which detects the over current conditions. For the case when another OVERCURz pin is used, this pin can be left unconnected. | |||||||||
| USB_SSTXP_DN3 | 19 | O | USB SuperSpeed transmitter differential pair (positive) | ||||||
| USB_SSTXM_DN3 | 20 | O | USB SuperSpeed transmitter differential pair (negative) | ||||||
| USB_SSRXP_DN3 | 22 | I | USB SuperSpeed receiver differential pair (positive) | ||||||
| USB_SSRXM_DN3 | 23 | I | USB SuperSpeed receiver differential pair (negative) | ||||||
| USB_DP_DN3 | 17 | I/O | USB High-speed differential transceiver (positive) | ||||||
| USB_DM_DN3 | 18 | I/O | USB High-speed differential transceiver (negative) | ||||||
| PWRCTL3/BATEN3 | 33 | I/O, PD | USB Port 3 Power On Control for Downstream Power/Battery Charging Enable. The pin is used for control of the downstream power switch for Port 3. This pin be left unconnected if power management is not implemented. | ||||||
| In addition, the value of the pin is sampled at the de-assertion of reset to determine the value of the battery charging support for Port 3 as indicated in the Battery Charging Support register: | |||||||||
| 0 = Battery charging not supported | |||||||||
| 1 = Battery charging supported | |||||||||
| OVERCUR3z | 44 | I, PU | USB Port 3 Over-Current Detection. This pin is typically connected to the over current output of the downstream port power switch for Port 3. | ||||||
| 0 = An over current event has occurred | |||||||||
| 1 = An over current event has not occurred | |||||||||
| When GANGED power management is enabled, this pin or one of the other OVERCURz pins must be connected to the over current output of the power switch or circuit which detects the over current conditions. For the case when another OVERCURz pin is used, this pin can be left unconnected. | |||||||||
| USB_SSTXP_DN4 | 26 | O | USB SuperSpeed transmitter differential pair (positive) | ||||||
| USB_SSTXM_DN4 | 27 | O | USB SuperSpeed transmitter differential pair (negative) | ||||||
| USB_SSRXP_DN4 | 29 | I | USB SuperSpeed receiver differential pair (positive) | ||||||
| USB_SSRXM_DN4 | 30 | I | USB SuperSpeed receiver differential pair (negative) | ||||||
| USB_DP_DN4 | 24 | I/O | USB High-speed differential transceiver (positive) | ||||||
| USB_DM_DN4 | 25 | I/O | USB High-speed differential transceiver (negative) | ||||||
| PWRCTL4/BATEN4 | 32 | I/O, PD | USB Port 4 Power On Control for Downstream Power/Battery Charging Enable. The pin is used for control of the downstream power switch for Port 4. This pin be left unconnected if power management is not implemented. | ||||||
| In addition, the value of the pin is sampled at the de-assertion of reset to determine the value of the battery charging support for Port 4 as indicated in the Battery Charging Support register: | |||||||||
| 0 = Battery charging not supported | |||||||||
| 1 = Battery charging supported | |||||||||
| OVERCUR4z | 43 | I, PU | USB Port 4 Over-Current Detection. This pin is typically connected to the over current output of the downstream port power switch for Port 4. | ||||||
| 0 = An over current event has occurred | |||||||||
| 1 = An over current event has not occurred | |||||||||
| When GANGED power management is enabled, this pin or one of the other OVERCURz pins must be connected to the over current output of the power switch or circuit which detects the over current conditions. For the case when another OVERCURz pin is used, this pin can be left unconnected. | |||||||||
| I2C/SMBUS I2C Signals | |||||||||
| SCL/SMBCLK | 38 | I/O, PD | I2C clock/SMBus clock. Function of pin depends on the setting of the SMBUSz input. | ||||||
| When SMBUSz = 1, this pin acts as the serial clock interface for an I2C EEPROM. | |||||||||
| When SMBUSz = 0, this pin acts as the serial clock interface for an SMBus host. | |||||||||
| Can be left unconnected if external interface not implemented. | |||||||||
| SDA/SMBDAT | 37 | I/O, PD | I2C data/SMBus data. Function of pin depends on the setting of the SMBUSz input. | ||||||
| When SMBUSz = 1, this pin acts as the serial data interface for an I2C EEPROM. | |||||||||
| When SMBUSz = 0, this pin acts as the serial data interface for an SMBus host. | |||||||||
| Can be left unconnected if external interface not implemented. | |||||||||
| SMBUSz/SS_SUSPEND | 39 | I/O, PU | I2C/SMBus mode select/SuperSpeed USB Suspend Status. The value of the pin is sampled at the de-assertion of reset set I2C or SMBus mode as follows: | ||||||
| 1 = I2C Mode Selected | |||||||||
| 0 = SMBus Mode Selected | |||||||||
| Can be left unconnected if external interface not implemented. | |||||||||
| After reset, this signal indicates the SuperSpeed USB Suspend status of the upstream port if enabled through the stsOutputEn bit in the Additional Feature Configuration register. When enabled, a value of 1 indicates the connection is suspended. | |||||||||
| Test and Miscellaneous Signals | |||||||||
| FULLPWRMGMTz/FULLAUTOz/SMBA1/SS_UP | 40 | I/O, PD | Full power management enable/SMBus address bit 1/SuperSpeed USB Connection Status Upstream port. | ||||||
| The value of the pin is sampled at the de-assertion of reset to set the power switch control follows: | |||||||||
| 0 = Power switching and over current inputs supported | |||||||||
| 1 = Power switching and over current inputs not supported | |||||||||
| Full power management is the ability to control power to the downstream ports of the TUSB8042A using PWRCTL[4:1]/BATEN[4:1]. | |||||||||
| If BATENx = 1 on any port, full power management must be enabled so the value of the terminal is sampled at the de-assertion to initialize the value of the FULLAUTOz bit. | |||||||||
| When AUTOENz = 0 and FULLAUTOz = 0: all ACP modes are supported. | |||||||||
| When AUTOENz = 0 and FULLAUTOz = 1:only highest current ACP mode is used in auto mode. | |||||||||
| When SMBus mode is enabled, this pin sets the value of the SMBus slave address bit 1. | |||||||||
| Can be left unconnected if full power management and SMBus are not implemented. | |||||||||
| After reset, this signal indicates the SuperSpeed USB connection status of the upstream port if enabled through the stsOutputEn bit in the Additional Feature Configuration register. When enabled a value of 1 indicates the upstream port is connected to a SuperSpeed USB capable port. | |||||||||
| Note: Power switching must be supported for battery charging applications. | |||||||||
| PWRCTL_POL | 41 | I/O, PU | Power Control Polarity. | ||||||
| The value of the pin is sampled at the de-assertion of reset to set the polarity of PWRCTL[4:1]. | |||||||||
| 0 = PWRCTL polarity is active low | |||||||||
| 1 = PWRCTL polarity is active high | |||||||||
| GANGED/SMBA2/HS_UP | 42 | I/O, PD | Ganged operation enable/SMBus Address bit 2/HS Connection Status Upstream Port. | ||||||
| The value of the pin is sampled at the de-assertion of reset to set the power switch and over current detection mode as follows: | |||||||||
| 0 = Individual power control supported when power switching is enabled | |||||||||
| 1 = Power control gangs supported when power switching is enabled | |||||||||
| When SMBus mode is enabled using SMBUSz, this pin sets the value of the SMBus slave address bit 2. | |||||||||
| After reset, this signal indicates the High-speed USB connection status of the upstream port if enabled through the stsOutputEn bit in Additional Feature Configuration register. When enabled, a value of 1 indicates the upstream port is connected to a High-speed USB capable port. | |||||||||
| Note: Individual power control must be enabled for battery charging applications. | |||||||||
| AUTOENz/HS_SUSPEND | 45 | I/O, PU | Automatic Charge Mode Enable/HS Suspend Status. | ||||||
| The value of the pin is sampled at the de-assertion of reset to determine if automatic mode is enabled as follows: | |||||||||
| 0 = Automatic Mode is enabled on ports that are enabled for battery charging when the hub is unconnected. Please note that CDP is not supported on Port 1 when operating in Automatic mode. | |||||||||
| 1 = Automatic Mode is disabled | |||||||||
| This value is also used to set the autoEnz bit in the Battery Charging Support Register. | |||||||||
| After reset, this signal indicates the High-speed USB Suspend status of the upstream port if enabled through the stsOutputEn bit in Additional Feature Configuration register. When enabled, a value of 1 indicates the connection is suspended. | |||||||||
| TEST | 49 | I | This pin is reserved for factory test. For normal operation, this pin requires an external pull down resistor to ground on PCB. Recommend 10k or stronger resistor. | ||||||
| Power and Ground Signals | |||||||||
| VDD | 5, 8, 13, 21, 28, 31, 51, 57 | PWR | 1.1-V power rail | ||||||
| VDD33 | 16, 34, 52, 63 | PWR | 3.3-V power rail | ||||||
| VSS (Thermal Pad) | PWR | Ground. Thermal pad must be connected to ground. | |||||||
| NC | 60 | — | No connect, leave floating | ||||||