10.1 Layout Guidelines

High-speed circuits demand careful attention to layout and component placement. To assure proper performance of the UC1525A follow these rules:

• Use a ground plane
• Damp or clamp parasitic inductive kick energy from the gate of driven MOSFETs. Do not allow the output pins to ring below ground. A series gate resistor or a shunt 1-A Schottky diode at the output pin will serve this purpose.
• Bypass V_IN, V_C, and V_REF. Use 0.1-µF monolithic ceramic capacitors with low equivalent series inductance. Allow less than 1 cm of total lead length for each capacitor between the bypassed pin and the ground plane.
• Treat the timing capacitor, C_T, like a bypass capacitor.

10.2 Layout Example

Figure 14. UC1525A Layout Example