8.3.1 UVLO

The UVLO circuit ensures that V_CC is adequate to make the UC184xA-SP fully operational before enabling the output stage. Figure 5 shows that the UVLO turnon and turnoff thresholds are fixed internally at 16 V and 10 V, respectively. The 6-V hysteresis prevents V_CC oscillations during power sequencing.

Figure 6 shows supply current requirements. Start-up current is < 1 mA for efficient bootstrapping from the rectified input of an off-line converter, as shown in Figure 7. During normal circuit operation, V_CC is developed from auxiliary winding, WAux, with D₁ and C_IN. However, at start-up, C_IN must be charged to 16 V through R_IN. With a start-up current of 1 mA, R_IN can be as large as 100 kΩ and still charge C_IN when VAc = 90-V RMS (low line). Power dissipation in R_IN would then be less than 350 mW even under high line (VAc = 130-V RMS) conditions.

During UVLO, the output driver is in a low state. While it does not exhibit the same saturation characteristics as normal operation, it can easily sink 1 mA, enough to ensure the MOSFET is held off.

Figure 5. UVLO Turnon TurnOff Threshold

During UVLO, the output driver is biased to sink minor amounts of current.

Figure 6. Supply Current Requirements

Figure 7. Providing Power to the UC184xA-SP