SGLS318A November   2005  – November 2015 UC2854B-EP

PRODUCTION DATA.  

  1. 1 Features
  2. 2 Applications
  3. 3 Description
  4. 4 Revision History
  5. 5 Description (continued)
  6. 6 Pin Configuration and Functions
  7. 7 Specifications
    1. 7.1 Absolute Maximum Ratings
    2. 7.2 ESD Ratings
    3. 7.3 Recommended Operating Conditions
    4. 7.4 Thermal Information
    5. 7.5 Electrical Characteristics
    6. 7.6 Typical Characteristics
  8. 8 Detailed Description
    1. 8.1 Overview
    2. 8.2 Functional Block Diagram
    3. 8.3 Feature Description
      1. 8.3.1 Multiply/Square and Divide
      2. 8.3.2 Voltage Amplifier
      3. 8.3.3 Current Amplifier
      4. 8.3.4 Miscellaneous
    4. 8.4 Device Functional Modes
  9. 9 Application and Implementation
    1. 9.1 Application Information
    2. 9.2 Typical Application
      1. 9.2.1 Design Requirements
      2. 9.2.2 Detailed Design Procedure
        1. 9.2.2.1  Switching Frequency
        2. 9.2.2.2  Inductor Selection
        3. 9.2.2.3  Output Capacitor
        4. 9.2.2.4  Switch and Diode
        5. 9.2.2.5  Current Sensing
        6. 9.2.2.6  Peak Current Limit
        7. 9.2.2.7  Multiplier Set-up
        8. 9.2.2.8  Feedforward Voltage
        9. 9.2.2.9  Multiplier Input Current
        10. 9.2.2.10 Oscillator Frequency
        11. 9.2.2.11 Current Error Amplifier Compensation
        12. 9.2.2.12 Voltage Error Amplifier Compensation
        13. 9.2.2.13 Feedforward Voltage Divider Filter Capacitors
        14. 9.2.2.14 Design Procedure Summary
      3. 9.2.3 Application Curve
  10. 10Power Supply Recommendations
  11. 11Layout
    1. 11.1 Layout Guidelines
    2. 11.2 Layout Example
  12. 12Device and Documentation Support
    1. 12.1 Community Resources
    2. 12.2 Trademarks
    3. 12.3 Electrostatic Discharge Caution
    4. 12.4 Glossary
  13. 13Mechanical, Packaging, and Orderable Information

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机械数据 (封装 | 引脚)
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订购信息

6 Pin Configuration and Functions

DW Package
16-Pin SOIC
Top View
UC2854B-EP po_sgls318.gif

Pin Functions

PIN I/O DESCRIPTION
NAME J/N/DW Q/L
CAO 3 4 O Output of the wide bandwidth current amplifier and one of the inputs to the PWM duty-cycle comparator. The output signal generated by this amplifier commands the PWM to force the correct input current. The output can swing from 0.1 V to 7.5 V.
CT 14 18 I Capacitor from CT to GND sets the PWM oscillator frequency
ENA 10 13 I A nominal voltage above 2.65 V on this pin allows the device to begin operating. Once operating, the device shuts off if this pin goes below 2.15 V nominal.
GND 1 2 — All bypass and timing capacitors connected to GND should have leads as short and direct as possible. All voltages are measured with respect GND.
GTDRV 16 20 O Output of the PWM is a 1.5-A peak totem-pole MOSFET gate driver on GTDRV. This output is internally clamped to 15 V so that the device can be operated with VCC as high as 35 V. Use a series gate resistor of at least 5 Ω to prevent interaction between the gate impedance and the GTDRV output driver that might cause the GTDRV output to overshoot excessively. Some overshoot of the GTDRV output is always expected when driving a capacitive load.
IAC 6 8 I Current input to the multiplier, proportional to the instantaneous line voltage. This input to the analog multiplier is a current. The multiplier is tailored for low distortion from this current input (IAC) to MOUT, so this is the only multiplier input that should be used for sensing instantaneous line voltage. The nominal voltage on ac is 6 V, so in addition to a resistor from IAC to rectified 60 Hz, connect a resistor from IAC to VREF. If the resistor to VREF is one-fourth of the value of the resistor to the rectifier, then the 6-V offset is cancelled, and the line current has minimal cross-over distortion.
ISENSE 4 5 I Switch current sensing input. This is the inverting input to the current amplifier. This input and the non-inverting input MOUT remain functional down to and below GND. Care should be taken to avoid taking these inputs below −0.5 V, because they are protected with diodes to GND.
MOUT 5 7 I/O Multiplier output and current sense plus. The output of the analog multiplier and the non-inverting input of the current amplifier are connected together at MOUT. The cautions about taking ISENSE below −0.5 V also apply to MOUT. As the multiplier output is a current, this is a high-impedance input similar to ISENSE, so the current amplifier can be configured as a differential amplifier to reject GND noise.
PKLMT 2 3 I Peak limit. The threshold for PKLMT is 0 V. Connect this input to the negative voltage on the current sense resistor. Use a resistor to REF to offset the negative current sense signal up to GND.
RSET 12 15 I Oscillator charging current and multiplier limit set. A resistor from RSET to ground programs oscillator charging current. Multiplier output current does not exceed 3.75 V divided by the resistor from RSET to ground.
SS 13 17 I Soft-start. SS remains at GND as long as the device is disabled or VCC is too low. SS pulls up to over 8 V by an internal 14-mA current source when both VCC becomes valid and the device is enabled. SS acts as the reference input to the voltage amplifier if SS is below VREF. With a large capacitor from SS to GND, the reference to the voltage regulating amplifier rises slowly, and increase the PWM duty cycle slowly. In the event of a disable command or a supply dropout, SS will quickly discharge to ground and disable the PWM.
VAO 7 9 I Voltage amplifier input
VCC 15 19 I Positive supply rail
VREF 9 12 O Used to set the peak limit point and as an internal reference for various device functions. This voltage must be present for the device to operate.
VRMS 8 10 I One of the inputs into the multiplier. This pin provides the input RMS voltage to the multiplier circuitry.
VSENSE 11 14 I This pin provides the feedback from the output. This input goes into the voltage error amplifier and the output of the error amplifier is another of the inputs into the multiplier circuit.
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