10.1 Layout Guidelines

• Place a low ESR and ESL decoupling capacitor C_REF in the 1-µF to 2.2-µF range, preferably ceramic, from VREF pin to GND.
• The EA+ is a non-inverting input, the EA– is an inverting input and the COMP is the output of the error amplifier. Place resistor and capacitor series network between EA+ pin and COMP pin, and reduce the trace of resistor and capacitor series network as much as possible.
• Place a low ESR and ESL capacitor C_T, preferably ceramic, from CT pin to GND, and place C_T close to UCx846/7 as much as possible.
• Place a resistor R_T from RT pin to GND, and place R_T close to UCx846/7 as much as possible.

10.2 Layout Example

Figure 12. UCx84x Layout Example