ZHCSM92A January   2021  – June 2021 UCC12051-Q1

PRODUCTION DATA  

  1. 1 特性
  2. 2 应用
  3. 3 说明
  4. 4 Revision History
  5. 5 Pin Configuration and Functions
  6. 6 Specifications
    1. 6.1  Absolute Maximum Ratings
    2. 6.2  ESD Ratings
    3. 6.3  Recommended Operating Conditions
    4. 6.4  Thermal Information
    5. 6.5  Power Ratings
    6. 6.6  Insulation Specifications
    7. 6.7  Safety-Related Certifications
    8. 6.8  Safety Limiting Values
    9. 6.9  Electrical Characteristics
    10. 6.10 Switching Characteristics
    11. 6.11 Insulation Characteristics Curves
    12. 6.12 Typical Characteristics
  7. 7 Detailed Description
    1. 7.1 Overview
    2. 7.2 Functional Block Diagram
    3. 7.3 Feature Description
      1. 7.3.1 Enable and Disable
      2. 7.3.2 UVLO, Power-Up, and Power-Down Behavior
      3. 7.3.3 VISO Load Recommended Operating Area
      4. 7.3.4 Thermal Shutdown
      5. 7.3.5 External Clocking and Synchronization
      6. 7.3.6 VISO Output Voltage Selection
      7. 7.3.7 Electromagnetic Compatibility (EMC) Considerations
    4. 7.4 Device Functional Modes
  8. 8 Application and Implementation
    1. 8.1 Application Information
    2. 8.2 Typical Application
      1. 8.2.1 Design Requirements
      2. 8.2.2 Detailed Design Procedure
        1. 8.2.2.1 VISO Output Capacitor Selection
      3. 8.2.3 Application Curves
  9. 9 Power Supply Recommendations
  10. 10Layout
    1. 10.1 Layout Guidelines
    2. 10.2 Layout Example
  11. 11Device and Documentation Support
    1. 11.1 Device Support
      1. 11.1.1 Development Support
    2. 11.2 Documentation Support
      1. 11.2.1 Related Documentation
    3. 11.3 接收文档更新通知
    4. 11.4 支持资源
    5. 11.5 Trademarks
    6. 11.6 Electrostatic Discharge Caution
    7. 11.7 术语表
  12. 12Mechanical, Packaging, and Orderable Information

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8.2.1 Design Requirements

To design using UCC12051-Q1, a few simple design considerations must be evaluated. Table 8-1 shows some recommended values for a typical application. See Power Supply Recommendations and Layout sections to review other key design considerations for the UCC12051-Q1 .

Table 8-1 Design Parameters
PARAMETER RECOMMENDED VALUE
Input supply voltage, VINP 4.5 V to 5.5 V
Decoupling capacitance between VINP and GNDP 10 µF, 16 V, ± 10%, X7R
Decoupling capacitance between VISO and GNDS (1) 10 µF, 16 V, ± 10%, X7R
Optional additional capacitance on VISO or VINP to reduce high-frequency ripple 0.1 µF, 50 V, ± 10%, X7R
Pull-up resistor from SYNC_OK to VINP, RPU 100 kΩ
Pull-up resistor from SEL to VISO for 5.0-V output voltage mode, RSEL 0 Ω
Pull-up resistor from SEL to VISO for 5.4-V output voltage mode, RSEL 100 kΩ
Optional SYNC signal impedance-matching resistor, RSYNC Match source — typical values are 50 Ω, 75 Ω, 100 Ω, or 1 kΩ
External clock signal applied on SYNC 16 MHz
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