The UCC14240-Q1 module uses an active full-bridge inverter on the primary-side and a passive full-bridge rectifier on the secondary-side. The small integrated transformer has a relatively high carrier frequency to reduce the size for integrating into the 36-pin SOIC package. The power stage carrier frequency operates within 10 MHz to 16 MHz. The power stage carrier frequency is determined by input voltage with a feed-forward control: when V_VIN is less than 21 V, the frequency is clamped at 16 MHz; when V_VIN is higher than 27 V, the frequency is clamped at 10 MHz; when V_VIN is between 21 V and 27 V, the frequency reduces gradually from 16 MHz to 10 MHz as V_VIN voltage rises. Spread spectrum modulation, SSM, is used to reduce emissions. ZVS operation is maintained to reduce switching power losses.

The UCC14240-Q1 module creates two regulated outputs. It can be configured as a single output converter, VDD to VEE only, or a dual-output converter, VDD to VEE and COM to VEE. Even though the module uses VEE as the reference point to create two positive output voltages, the outputs can use COM as the reference point and become a positive and a negative output.

These two outputs are controlled independently through hysteresis control. Furthermore, the VDD-VEE is the main output, and COM to VEE uses the main output as its input to created a second regulated output voltage.