米6体育平台手机版

ZHCSOX6C September 2021 – December 2022 UCC14240-Q1

PRODUCTION DATA

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机械数据 (封装 | 引脚)

DWN|36
- MPSS132

散热焊盘机械数据 (封装 | 引脚)

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6.8 Electrical Characteristics

Over operating temperature range (–40 °C ≤ T_J ≤ 150 °C, 21 V ≤ V_VIN ≤ 27 V, C_IN = 10µF, C_OUT = 2.2 µF, V_ENA = 5 V, R_LIM = 1 kΩ, unless otherwise noted. All typical values at T_A = 25 °C and V_VIN = 24 V.

PARAMETER		TEST CONDITIONS	MIN	TYP	MAX	UNIT
INPUT SUPPLY (Primary-side. All voltages with respect to GNDP)
V_VIN	Input voltage range	Primary-side input voltage to GNDP	21	24	27	V
I_{VINQ_OFF}	VIN quiescent current, disabled	V_ENA=0 V; V_VIN = 21 V - 27 V			700	µA
I_{VIN_ON_NO_LOAD}	VIN operating current, enabled, No Load	V_ENA = 5 V; V_VIN = 21 V - 27 V; (VDD – VEE) = 25-V regulating; I_{VDD – VEE} = 0 mA			35	mA
I_{VIN_ON_FULL_LOAD}	VIN operating current, enabled, Full Load	V_ENA=5 V; V_VIN = 21 V - 27 V; (VDD – VEE) = 25-V regulating; I_{VDD – VEE} = 60 mA			250	mA
UVLOP COMPARATOR (Primary-side. All voltages with respect to GNDP)
V_{VIN_ANALOG_UVLOP_RISING}	VIN analog undervoltage lockout rising threshold		8	9	10	V
V_{VIN_ ANALOG_UVLOP_FALLING}	VIN analog undervoltage lockout falling threshold		7	8	9	V
V_{VIN_UVLOP_RISING}	VIN undervoltage lockout rising threshold		19	20	21	V
V_{VIN_UVLOP_FALLING}	VIN undervoltage lockout falling threshold		17.1	18	18.9	V
OVLO COMPARATOR (Primary-side. All voltages with respect to GNDP)
V_{VIN_OVLO_RISE}	VIN overvoltage lockout rising threshold		29.45	31	32.55	V
V_{VIN_OVLO_FALLING}	VIN overvoltage lockout falling threshold		27.55	29	30.45	V
THERMAL SHUTDOWN COMPARATOR (Primary-side)
TSHUTP_{PRIMARY_RISE}	Primary-side over-temperature shutdown rising threshold ⁽¹⁾	First time at power-up Tj needs to be < 130 °C to turn on	140	150	160	°C
TSHUTP_{PRIMARY_HYST}	Primary-side over-temperature shutdown hysteresis ⁽¹⁾		15	20	25	°C
ENA INPUT PIN (Primary-side. All voltages with respect to GNDP)
V_{EN_IR}	Input voltage rising threshold, logic HIGH	Rising edge			2.1	V
V_{EN_IF}	Input voltage falling threshold, logic LOW	Falling edge	0.8			V
I_EN	Enable Pin Input Current	V_ENA = 5.0 V		5	10	µA
PG OPEN-DRAIN OUTPUT PIN (Primary-side. All voltages with respect to GNDP)
V_{PG_OUT_LO}	PG output-low saturation voltage	Sink Current = 5 mA, power good			0.5	V
I_{PG_OUT_HI}	PG Leakage current	V_PG = 5.5 V, power not good			5	µA
F_SW	Switching frequency	V_VIN = 24 V; V_ENA = 5 V; (VDD-VEE) = 25 V	11	13	15	MHz
F_SSM	Frequency of Spread Spectrum Modulation (SSM) triangle waveform	Only during primary-side startup starting after VIN > UVLOP, and ENA = HIGH; F_{SS_BURST_P} = 1/8 µs = 125 kHz		90		kHz
SSM Percentage change of F_CARRIER	SSM Percent change of carrier frequency during Spread Spectrum Modulation (SSM) by triangle waveform	Only during primary-side startup starting after VIN > UVLOP, and ENA = HIGH; F_{SS_BURST_P} = 1/8 µs = 125 kHz		5		%
t_{SOFT_START_TIME_OUT}	Primary-side soft-start time-out	Timer begins when VIN > UVLOP and ENA = High and reset when Powergood pin indicates Good		16		ms
VDD OUTPUT VOLTAGE (Secondary-side. All voltages with respect to VEE)
V_{VDD_RANGE}	(VDD – VEE) Output voltage range		18		25	V
V_{VDD_DC_ACCURACY}	(VDD – VEE) Output voltage DC regulation accuracy	Secondary-side (VDD – VEE) output voltage, over load, line and temperature range, externally adjust with external resistor divider	-1.3		1.3	%
VDD REGULATION HYSTERETIC COMPARATOR (Secondary-side. All voltages with respect to VEE)
V_{FBVDD_REF}	Feedback regulation reference voltage for (VDD – VEE)	(VDD – VEE) output in regulation	2.4675	2.5	2.5325	V
V_{FBVDD_HYST}	FBVDD Hysteresis comparator hysteresis settings. Hysteresis at the FBVDD pin. [The (VDD-VEE) hysteresis would amplify this FBVDD hysteresis by the feedback resistor divider gain.]		9	10	12.3	mV
COM OUTPUT VOLTAGE (Secondary-side. All voltages with respect to VEE)
V_{VEE_RANGE}	(COM – VEE) Output voltage range		2.5		(VDD – VEE)	V
V_{VEE_DC_ACCURACY}	(COM – VEE) Output voltage DC regulation accuracy	Secondary-side (COM – VEE) output voltage, over load, line and temperature range, externally adjust with external resistor divider	–1.3		1.3	%
COM REGULATION HYSTERETIC COMPARATOR (Secondary-side. All voltages with respect to VEE)
V_{FBVEE_REF}	Feedback regulation reference voltage for (COM – VEE)	(COM – VEE) output in regulation	2.4675	2.5	2.5325	V
V_{RLIM_SHORT_CHRG_CMP_RISE}	RLIM pin Short Charge comparator rising threshold to exit PWM	Rising threshold		0.73		V
t_{RLIM_SHORT_CHRG_ON_TIME}	On-Time during RLIM pin Short Charge PWM mode	RLIM pin < 0.645 V, while FBVEE pin < 2.48 V		1.2		us
t_{RLIM_SHORT_CHRG_OFF_TIME}	Off-Time during RLIM pin Short Charge PWM mode	RLIM pin < 0.645 V, while FBVEE pin < 2.48 V		5		us
UVLOS COMPARATOR (Secondary-side. All voltages with respect to VEE)
V_{VDD_UVLO_RISE}	(VDD – VEE) undervoltage lockout rising threshold	Voltage at FBVDD		0.9		V
V_{VDD_UVLO_HYST}	(VDD – VEE) undervoltage lockout hysteresis	Voltage at FBVDD		0.2		V
OVLOS COMPARATOR (Secondary-side. All voltages with respect to VEE)
V_{VDD_OVLOS_RISE}	(VDD – VEE) overvoltage lockout rising threshold	Voltage from VDD to VEE, rising	29.45	31	32.55	V
V_{VDD_OVLOS_FALLING}	(VDD – VEE) overvoltage lockout falling threshold	Voltage from VDD to VEE, falling	27.55	29	30.45	V
SOFT-START (Secondary-side. All voltages with respect to VEE)
VREF_Voltage_per_Steps	Voltage per step	7 Steps of 200mV each, starting from 1.3V and ending at 2.5V.		0.2		V
VREF_Voltage_Start	VREF voltage at Start of secondary-side soft-start	7 Steps of 200mV each, starting from 1.3V and ending at 2.5V.		1.3		V
VREF_Voltage_End	VREF voltage at End of secondary-side soft-start	7 Steps of 200mV each, starting from 1.3V and ending at 2.5V.		2.5		V
UVP1, (VDD – VEE) UNDER -VOLTAGE PROTECTION COMPARATOR (Secondary-side. All voltages with respect to VEE)
V_{VDD_UVP_RISE}	(VDD – VEE) under-voltage protection rising threshold, V_UVP = V_REF× 90%		2.175	2.25	2.35	V
V_{VDD_UVP_HYST}	(VDD – VEE) undervoltage protection hysteresis			20		mV
OVP1, (VDD – VEE) OVER-VOLTAGE PROTECTION COMPARATOR (Secondary-side. All voltages with respect to VEE)
V_{VDD_OVP_RISE}	(VDD – VEE) over-voltage protection rising threshold, V_OVP = V_REF×110%		2.7	2.75	2.825	V
V_{VDD_OVP_HYST}	(VDD – VEE) overvoltage protection hysteresis			20		mV
UVP2, (COM – VEE) UNDER -VOLTAGE PROTECTION COMPARATOR (Secondary-side. All voltages with respect to VEE)
V_{VEE_UVP_RISE}	(COM – VEE) under-voltage protection rising threshold, V_UVP = V_REF× 90%		2.1	2.25	2.4	V
V_{VEE_UVP_HYST}	(COM – VEE) undervoltage protection hysteresis			20		mV
OVP2, (COM – VEE) OVER-VOLTAGE PROTECTION COMPARATOR (Secondary-side. All voltages with respect to VEE)
V_{VEE_OVP_RISE}	(COM – VEE) over-voltage protection rising threshold, V_OVP = V_REF× 110%		2.7	2.75	2.825	V
V_{VEE_OVP_HYST}	(COM – VEE) over-voltage protection hysteresis			20		mV
THERMAL SHUTDOWN COMPARATOR (Secondary-side)
TSHUTS_{SECONDARY_RISE}	Secondary -side over-temperature shutdown rising threshold ⁽¹⁾	First time at power-up Tj needs to be < 130^oC to turnon.	145	150	155	°C
TSHUTS_{SECONDARY_HYST}	Secondary-side over-temperature shutdown hysteresis ⁽¹⁾		15	20	25	°C
CMTI (Common Mode Transient Immunity)
CMTI	Common Mode Transient Immunity	Positive VEE with respect to GNDP	150			V/ns
CMTI	Common Mode Transient Immunity	Negative VEE with respect to GNDP			–150	V/ns
INTEGRATED TRANSFORMER (Primary-side to Secondary-side)
N	Transformer effective turns ratio	Secondary side to primary side		1.18		-

(1) Functionality tested in production. MIN, TYP, MAX ensured by characterization.