8.3.3 Input Stage

The input pins (PWM and DIS) of the UCC20225-Q1 family are based on a TTL and CMOS compatible input-threshold logic that is totally isolated from the VDD supply voltage. The input pins are easy to drive with logic-level control signals (such as those from 3.3-V micro-controllers), since UCC20225-Q1 family has a typical high threshold (V_PWMH) of 1.8 V and a typical low threshold of 1 V, which vary little with temperature (see Figure 22,Figure 23). A wide hysteresis (V_{PWM_HYS}) of 0.8 V makes for good noise immunity and stable operation. If any of the inputs are ever left open, internal pull-down resistors force the pin low. These resistors are typically 200 kΩ (See Functional Block Diagram). However, it is still recommended to ground an input if it is not being used for improved noise immunity.

Since the input side of UCC20225-Q1 family is isolated from the output drivers, the input signal amplitude can be larger or smaller than VDD, provided that it doesn’t exceed the recommended limit. This allows greater flexibility when integrating with control signal sources, and allows the user to choose the most efficient VDD for any gate. That said, the amplitude of any signal applied to PWM must never be at a voltage higher than VCCI.