Figure 10-1 shows a 2-layer PCB layout example with the signals and key components labeled.

Figure 10-1 Layout Example

Figure 10-2 and Figure 10-3 shows top and bottom layer traces and copper.

PCB traces between the high-side and low-side gate drivers in the output stage are increased to maximize the creepage distance for high-voltage operation, which will also minimize cross-talk between the switching node VSSA (SW), where high dv/dt may exist, and the low-side gate drive due to the parasitic capacitance coupling.

Figure 10-2 Top Layer Traces and Copper

Figure 10-3 Bottom Layer Traces and Copper

Figure 10-4 and Figure 10-5 are 3D layout pictures with top view and bottom views.

Figure 10-4 3-D PCB Top View

Figure 10-5 3-D PCB Bottom View