Low-ESR and low-ESL capacitors must be connected close to the device between the VCCI and GND pins and between the VDD and VSS pins to support high peak currents when turning on the external power transistor.
To avoid large negative transients on the switch node VSSA (HS) pin, the parasitic inductances between the source of the top transistor and the source of the bottom transistor must be minimized.
It is recommended to bypass using a ≥1-nF low ESR/ESL capacitor, CDIS, close to DIS pin when connecting to a μC with distance