The UCC21222-Q1 has an internal under voltage lock out (UVLO) protection feature on each supply voltage between the VDD and VSS pins for both outputs. When the VDD bias voltage is lower than V_{VDD_ON} at device start-up or lower than V_{VDD_OFF} after start-up, the VDD UVLO feature holds the channel output low, regardless of the status of the input pins.

When the output stages of the driver are in an unbiased or UVLO condition, the driver outputs are held low by an active clamp circuit that limits the voltage rise on the driver outputs (illustrated in Figure 7-1). In this condition, the upper PMOS is resistively held off by R_Hi-Z while the lower NMOS gate is tied to the driver output through R_CLAMP. In this configuration, the output is effectively clamped to the threshold voltage of the lower NMOS device, typically around 1.5V, regardless of whether bias power is available.

Figure 7-1 Simplified Representation of Active Pull Down Feature

The VDD UVLO protection has a hysteresis feature (V_{VDD_HYS}). This hysteresis prevents chatter when there is ground noise from the power supply. This also allows the device to accept small drops in bias voltage, which commonly occurs when the device starts switching and operating current consumption increases suddenly.

The inputs of the UCC21222-Q1 also have an internal under voltage lock out (UVLO) protection feature. The inputs cannot affect the outputs unless the supply voltage VCCI exceeds V_{VCCI_ON} on start-up. The outputs are held low and cannot respond to inputs when the supply voltage VCCI drops below V_{VCCI_OFF} after start-up. Like the UVLO for VDD, there is hystersis (V_{VCCI_HYS}) to ensure stable operation.