Whenever the supply voltage VCCI crosses from below the falling threshold V_{VCCI_OFF} to above the rising threshold V_{VCCI_ON}, and whenever the supply voltage VDDx crosses from below the falling threshold V_{VDDx_OFF} to above the rising threshold V_{VDDx_ON}, there is a delay before the outputs begin responding to the inputs. For VCCI UVLO this delay is defined as t_{VCCI+ to OUT}, and has a maximum value of 50 µs. For VDDx UVLO this delay is defined as t_{VDD+ to OUT}, and has a maximum value of 10 µs. TI recommends allowing some margin before driving input signals, to ensure the driver VCCI and VDD bias supplies are fully activated. Figure 7-7 and Figure 7-8 show the power-up UVLO delay timing diagram for VCCI and VDD.

Whenever the supply voltage VCCI crosses below the falling threshold V_{VCCI_OFF}, or VDDx crosses below the falling threshold V_{VDDx_OFF}, the outputs stop responding to the inputs and are held low within ≤2 µs. This asymmetric delay is designed to ensure safe operation during VCCI or VDDx brownouts.

When VCCI goes away but VDDx is present, outputs are held low; when VDDx is gone, outputs are CLAMPED low through the active pull down feature. For more detailed UVLO feature description, please check session Section 8.3.1.

Figure 7-7 VCCI Power-up UVLO Delay

Figure 7-8 VDDA/B Power-Up UVLO Delay