The UCC21717-Q1 features split outputs OUTH and OUTL, which enables independent control of the turn on and turn off switching speeds. The turn on and turn off resistances determine the peak source and sink currents, which control the switching speed in turn. Meanwhile, power dissipation in the gate driver should be considered to ensure the device is in the thermal limit. At first, the peak source and sink currents are calculated as:

Equation 1.

Where

• R_{OH_EFF} is the effective internal pull-up resistance of the hybrid pull-up structure, which is approximately 2 x R_OL, about 0.7 Ω.
• R_OL is the internal pulldown resistance, about 0.3 Ω.
• R_ON is the external turn on gate resistance.
• R_OFF is the external turn off gate resistance.
• R_{G_Int} is the internal resistance of the SiC MOSFET or IGBT module.

Figure 9-5 Output Model for Calculating Peak Gate Current

For example, for an IGBT module based system with the following parameters:

• Q_g = 3300 nC
• R_{G_Int} = 1.7 Ω
• R_ON=R_OFF= 1 Ω

The peak source and sink currents in this case are:

Equation 2.

Thus by using a 1-Ω external gate resistance, the peak source current is 5.9 A and the peak sink current is 6.7 A. The collector-to-emitter dV/dt during the turn on switching transient is dominated by the gate current at the Miller plateau voltage. The hybrid pullup structure ensures the peak source current at the Miller plateau voltage, unless the turn on gate resistor is too high. The faster the collector-to-emitter, V_ce, voltage rises to V_DC, the smaller the turn on switching loss is. The dV/dt can be estimated as Q_gc/I_{source_pk}. For the turn off switching transient, the drain-to-source dV/dt is dominated by the load current, unless the turn off gate resistor is too high. After V_ce reaches the dc bus voltage, the power semiconductor is in saturation mode and the channel current is controlled by V_ge. The peak sink current determines the dI/dt, which dominates the V_ce voltage overshoot accordingly. If using relatively large turn off gate resistance, the V_ce overshoot can be limited. The overshoot can be estimated by:

Equation 3.

Where

• L_stray is the stray inductance in power switching loop, as shown in Figure 9-6
• I_load is the load current, which is the turn off current of the power semiconductor.
• C_ies is the input capacitance of the power semiconductor.
• V_plat is the plateau voltage of the power semiconductor.
• V_th is the threshold voltage of the power semiconductor.

Figure 9-6 Stray Parasitic Inductance of IGBTs in a Half-Bridge Configuration

Power dissipation should be taken into account to maintain the gate driver within the thermal limit. The power loss of the gate driver includes the quiescent loss and the switching loss, which can be calculated as:

Equation 4.

P_Q is the quiescent power loss for the driver, which is I_q x (VDD-VEE) = 5 mA x 20 V = 0.100 W. The quiescent power loss is the power consumed by the internal circuits such as the input stage, reference voltage, logic circuits, protection circuits when the driver is switching when the driver is biased with VDD and VEE, and also the charging and discharging current of the internal circuit when the driver is switching. The power dissipation when the driver is switching can be calculated as:

Equation 5.

Where

• Q_g is the gate charge required at the operation point to fully charge the gate voltage from VEE to VDD.
• f_sw is the switching frequency.

In this example, the P_SW can be calculated as:

Equation 6.

Thus, the total power loss is:

Equation 7.

When the board temperature is 125°C, the junction temperature can be estimated as:

Equation 8.

Therefore, for the application in this example, with 125°C board temperature, the maximum switching frequency is ~50 kHz to keep the gate driver in the thermal limit. By using a lower switching frequency, or increasing external gate resistance, the gate driver can be operated at a higher switching frequency.