ZHCSNL4A August 2020 – March 2021 UCC23511-Q1
PRODUCTION DATA
The external gate-driver resistors, RG(ON) and RG(OFF) are used to:
The output stage of UCC23511-Q1 has a pull up structure consisting of a P-channel MOSFET and an N-channel MOSFET in parallel, as shown in Figure 8-4. The N-channel MOSFET provides the peak current that charges the gate of the IGBT (or power switch) while the P-channel MOSFET ensures that VOUT will go all the way upto VCC. Figure 10-1 shows the internal gate resistance, RG_int of the power switch. RG_int is usually specified in the datasheet of the power switch. When turning the power switch "on", the gate driver sees a total gate resistance RG_total = RGON + RG_int and when turning the power switch "off", the gate driver sees a total gate resistance RG_total = RGOFF + RG_int in series with the gate capacitance where,
To illustrate the procedure to select RGON and RGOFF , let us consider the following example with the assumptions listed below:
For this example, since VCC=15V, use the typical curves shown in Figure 10-5. It can be seen that we need a total turn on resistance of 7 ohms (peak charging current of 1.5A) and a total turn off resistance of 8 ohms (peak discharging current of 1.7A). Subtracting the internal gate resistance of the power switch, we get RGON= 7 ohms - 2 ohms = 5 ohms, and RGOFF= 8 ohms- 2 ohms = 6 ohms.
Use Table 10-3 to find the minimum gate resistance to be used with UCC23511-Q1 when driving a power switch. The values shown includes the power switch internal gate resistance RG_int. Hence, RG_int must be subtracted from the values shown to determine the value of the resistor to populate on the printed circuit board.
Gate driver supply VCC-VEE (V) | Minimum total gate resistance (Ω) = (RGON+ RG_int) or (RGOFF+ RG_int) |
---|---|
15 | 4 |
23 | 7 |
30 | 10 |
The diodes shown in series with each, RGON and RGOFF, in Figure 10-1 ensure the gate drive current flows through the intended path, respectively, during turn-on and turn-off. Note that the diode forward drop will reduce the voltage level at the gate of the power switch. To achieve rail-to-rail gate voltage levels, add a resistor from the VOUT pin to the power switch gate, with a resistance value approximately 20 times higher than RGON and RGOFF. For the examples described in this section, a good choice is 100 Ω to 200 Ω.
The estimated peak current is also influenced by PCB layout and load capacitance. Parasitic inductance in the gate-driver loop can slow down the peak gate-drive current and introduce overshoot and undershoot. Therefore, TI strongly recommends that the gate-driver loop should be minimized. Conversely, the peak source and sink current is dominated by loop parasitics when the load capacitance (CISS) of the power transistor is very small (typically less than 1 nF) because the rising and falling time is too small and close to the parasitic ringing period.