7.3.4 Gate Voltage Clamping

With the wide VDD voltage range capability, UCC24612 clamps the gate driver voltage to a maximum level of 9.5 V to allow fast driving speed, low driving loss and compatibility with different MOSFETs. The 9.5-V level is chosen to minimize the conduction loss for the non-logic level MOSFETs.

The gate driver voltage clamp is achieved through the regulated REG pin voltage. When VDD voltage is above 9.5 V, the linear regulator regulates the REG pin voltage to be 9.5 V, which is also the power supply of the gate driver stage. This way, the MOSFET gate is clamped at 9.5 V, regardless of how high the VDD voltage is. When the VDD voltage is close to or below the programmed REG pin regulation voltage, UCC24612 can no longer regulate the REG pin voltage. Instead, it enters a pass-through mode where the REG pin voltage follows the VDD pin voltage with slight voltage drop out (VREG_DO). During this time, the gate driver voltage is lower than its programmed value but still provides SR driving capability. The UCC24612 is disabled once the REG pin voltage drops below its UVLO level.