ZHCSDK6A March 2015 – March 2015 UCC24630
PRODUCTION DATA.
10 Layout
10.1 Layout Guidelines
In general, try to keep all high current loops as short as possible. Keep all high current/high frequency traces away from other traces in the design. If necessary, high-frequency/high-current traces should be perpendicular to signal traces, not parallel to them. Shielding signal traces with ground traces can help reduce noise pick up. Always consider appropriate clearances between the high-voltage connections and any low-voltage nets.
10.1.1 VDD Pin
The VDD pin must be decoupled to GND with good quality, low ESR, low ESL ceramic bypass capacitors with short traces to the VDD and GND pins. The value of the required capacitance on VDD is determined as shown in Section 7.3 . To eliminate high-frequency ripple current in the SR control circuit, it is recommended to place a small value resistance of 2.2 Ω to 10 Ω between VDD and the converter output voltage.
10.1.2 VPC Pin
The trace between the resistor divider and the VPC pin should be as short as possible to reduce/eliminate possible noise coupling. The lower resistor of the resistor divider network connected to the VPC pin should be returned to GND with short traces. Avoid adding any significant external capacitance to the VPC pin so that there is no delay of signal. If filtering is necessary a recommended maximum capacitance is 10 pF with a lower resistor divider network value of 10 kΩ. Avoid high dV/dt traces close to the VPC pin and connection trace such as the SR MOSFET drain and DRV output.
10.1.3 VSC Pin
The trace between the resistor divider and the VSC pin should be as short as possible to reduce/eliminate possible noise coupling. The lower resistor of the resistor divider network connected to the VSC pin should be returned to GND with short traces. Avoid adding any external capacitance to the VPC pin so that there is no delay of signal. If filtering is necessary a recommended maximum capacitance is 47 pF with a lower resistor divider network value of 50 kΩ. Avoid high dV/dt traces close to the VSC pin and connection trace such as the SR MOSFET drain and DRV output.
10.1.4 GND Pin
The GND pin is the power and signal ground connection for the controller. The effectiveness of the filter capacitors on the signal pins depends upon the integrity of the ground return. Place all decoupling capacitors as close as possible to the device pins with short traces. The device ground and power ground should meet at the output bulk capacitor’s return. Try to ensure that high frequency/high current from the power stage does not go through the signal ground.
10.1.5 TBLK Pin
The programming resistor is placed on TBLK to GND, with short traces. The value may have to be adjusted based on the time delay required. Avoid high dV/dt traces close to the TBLK pin and connection trace such as the SR MOSFET drain and DRV output.
10.1.6 DRV Pin
The track connected to DRV carries high dv/dt signals. Minimize noise pickup by routing the trace to this pin as far away as possible from tracks connected to the device signal inputs, VPC, VSC, and TBLK.
10.2 Layout Example
