7.3.1 Start Up and UVLO

The UCC24630 features a wide operating VDD range and low UVLO thresholds. The start up of the device is dependent on voltage levels on three pins: VDD, VPC and VSC. The VDD pin can be directly connected to the power supply output on converters from 5-V to 24-V nominal outputs. The start UVLO threshold is V_VDD(on), 4.0 V typical, and stop threshold is V_VDD(off), 3.6 V typical. The DRV output is not enabled unless the voltage on the VPC pin is greater than V_VPCEN for a time longer than t_VPC-BLK and the voltage on the VSC pin is greater than V_VSCEN. Once the VDD, VSC and VPC voltage and time thresholds are met, there is an internal initialization time and a four-cycle-initialization start sequence before the DRV output is enabled.

Refer to Figure 13 for a startup sequence that illustrates the timing sequence and configurable DRV output based on VDD level. In most converter designs, the conditions for the VPC and VSC voltage to enable the device are met before the VDD start-voltage threshold, this is reflected in the timing diagram. When VDD exceeds V_VDD(on) UVLO threshold the device starts the initialization sequence of 150 µs to 250 µs illustrated as t_INITIALIZE. After the device initialization, there is a logic initialization of 20 µs at which time V_TBLK is enabled (high). After the device is enabled, the CCM dead-time block requires four cycles to initialize the dead-time control before the DRV output is enabled. At VDD < V_PMOS the driver high-side PMOS device is enabled and the DRV peak will be close to VDD. When VDD exceeds V_PMOS the PMOS device is disabled and the driver is operating as a high-side NMOS only and DRV is approximately 1.2 V to 1.5 V lower than VDD. As VDD continues to increase, the DRV output is limited to V_DRCL regardless of VDD up to the recommended maximum rating.

Figure 13. Start-Up Operation

7.3.2 Volt-Sec SR Driver On-Time Control

Refer to the timing diagrams in Figure 14 and Figure 15 for functional details of the UCC24630 volt-sec on-time control.

Figure 14. Operation in DCM

Figure 15. Operation in CCM

The UCC24630 uses the VPC and VSC pins to sense the SR MOSFET V_DS voltage and converter V_OUT voltage through resistor dividers. The information of V_IN/N_PS, t_PRI, and V_OUT can be obtained from the information on VPC and VSC pins. The SR MOSFET turn on is determined when the SR MOSFET body diode starts conducting and the VPC pin voltage falls to near zero; the SR MOSFET turn off is determined by the current emulator control ramps. The SR timing determined by the volt-sec balance function is the dominant mode of operation with all flyback converters, including CCM.

The UCC24630 volt-sec control generates the internal VPC ramp and VSC ramp to emulate the transformer Volt-Sec balancing as shown in Figure 14 and Figure 15.

The secondary current discharge time, t_SEC-DIS can be determined indirectly. The primary volt-sec ramp and secondary volt-sec ramp both start when VPC rises above V_VPC-EN and V_VPC-TH. The charge currents for the VPC and VSC ramps are determined by the voltage on the VPC and VSC pins respectively.

When VPC is higher than V_VPC-EN and V_VPC-TH for t > t_VPC-BLK, the VPC pulse is qualified as a primary conduction pulse and the SR can be enabled on the VPC falling edge. The VPC ramp continues to rise until the VPC falling edge based on the real time voltage on the VPC pin and holds the peak for the cycle. The DRV output is turned on during the VPC falling edge near zero volts, and DRV is turned off when the VSC rising ramp crosses the VPC ramp held level.

Both VPC and VSC ramps are reset to zero on each VPC rising edge above the V_VPC-EN and V_VPC-TH thresholds.

To discriminate primary on-time pulses from DCM ringing, there are voltage and time criteria that must be satisfied on the VPC pin to enable the DRV output. t_VPC-BLK can be adjusted through the resistor on TBLK pin.

At the rising edge of VPC when the voltage exceeds V_VPC-EN and V_VPC-TH the blanking time t_VPC-BLK is initiated. At the end of t_VPC-BLK, the VPC voltage is sampled during t_VPC-SPL window, which is 100 ns nominal. Also at the end of t_VPC-BLK, the DRV output can be enabled.

The VPC voltage sampled during t_VPC-SPL determines the VPC dynamic threshold V_VPC-TH which is normally 85% of the sampled VPC voltage. The dynamic threshold provides the ability to reject the DCM ringing and detect the primary on-time. Noise immunity during the turn-on event of DRV at the falling edge of the VPC pin is enhanced by a minimum DRV on time of t_SRONMIN, which is 350 ns nominal.

During the falling edge of DRV, the t_OFF timer is initiated which inhibits turn on of the SR until t_OFF expires. This eliminates false turn on of DRV if the DCM ringing is close to ground.

The UCC24630 is designed to operate in a variety of flyback converter applications over a wide operating range. The internal volt-sec control ramps do have a dynamic range limit based on volt-sec on the VPC pin. As shown in Figure 16, a Volt-sec product exceeding 7 V-µs on the VPC pin will result in saturation of the VPC volt-sec control ramp. Operation beyond this point results in a DRV on-time less than expected. For example, if V_VPC = 0.5 V, t_VPC should be < 14 µs, or if V_VPC = 2.0 V, t_VPC should be < 3.5 µs, to operate within the dynamic range of the device. Assuming a converter operating in transition mode at low line and full load with a 50% duty cycle, the operating period is 28 µs which results in a frequency that is under 40 kHz. The UCC24630 low-frequency operating range extends to the standby mode threshold of 5 kHz; but each switching cycle V_VPC Volt-sec product should be less than 7 V-µs.

The device can support switching frequencies exceeding 200 kHz but the following timing limits need to be confirmed to be compatible with the power train. The minimum primary on time when the device is expected to be active needs to be compatible with the minimum VPC blanking time (t_VPC-BLK) setting of 203 ns plus the sampling window (t_VPC-SPL) of 100 ns. The minimum secondary current conduction time should be less than the minimum SR on time (t_SR(min)) of 350 ns. The minimum time from the SR drive turn off until the next SR drive turn on should be greater than the SR minimum off time (t_OFF) of 2.5 µs.

Figure 16. Ratio_{VPC_VSC} vs VPC V-µs

Figure 17. SR Controller Components

Determining the VPC and VSC divider resistors is based on the operating voltage ranges of the converter and Ratio_VPC-VSC gain ratio. Referring to Figure 17, the following equation determines the VPC divider values.

For R2 a value of 10 kΩ is recommended for minimal impact on time delay, and low-resistor dissipation. A higher R2 value reduces resistor divider dissipation but may increase the DRV turn-on delay due to the time constant of ~2 pF pin capacitance and divider resistance. A lower R2 value can be used with the tradeoff of higher dissipation in the resistor divider. A factor of 10% over the VPC threshold, V_VPCEN, is shown in Equation 1 for design margin.

Equation 1.

where

• V_IN(min) is the converter minimum primary bulk capacitor voltage.
• V_OUT(min) is the minimum converter output voltage in normal operation.
• V_VPCEN is the VPC enable threshold, use the specified maximum value.
• N_PS is the transformer primary to secondary turns ratio.

The operating voltage range on the VPC pin should be within the range of 0.45 V < V_VPC < 2 V. Referring to Figure 6, if V_VPC is greater than 2.3 V the dynamic range is exceeded and Ratio_{VPC_VSC} is reduced; in this condition the DRV on time is less than expected. If V_VPC is greater than 2.6 V for 500 ns, a fault is generated and DRV is disabled for the cycle, refer to Pin Fault Protection. To ensure the maximum voltage is within range confirm with Equation 2.

Equation 2.

where

• V_IN(max) is the converter maximum primary bulk capacitor voltage.
• V_OUT(max) is the maximum converter output voltage at OVP.
• N_PS is the transformer primary-to-secondary turns ratio.

The program voltage on the VSC pin is determined by the VPC divider ratio and the device's parameter Ratio_{VPC_VSC}. The current emulator ramp gain is higher on the VPC pin by the multiple Ratio_{VPC_VSC}, so the VSC resistor divider ratio is reduced by the same Ratio_{VPC_VSC} accordingly. Determine the VSC divider resistors using equation 3 below. To minimize resistor divider dissipation, a recommended range for R4 is 25 kΩ to 50 kΩ. Higher R4 values results in increasing offset due to VSC input current, I_VSC. Lower R4 values increases the resistor divider dissipation. To ensure DRV turn off slightly before the secondary current reaches zero, 10% margin is shown for initial values. Use a nominal value of 4.15 for Ratio_{VPC_VSC}.

Equation 3.

where

• Ratio_{VPC_VSC} is the device parameter VPC and VSC gain ratio, use a value of 4.15.

The operating voltage on the VSC pin should be within the range of 0.3 V < V_VSC < 2 V. Referring to Figure 7, if V_VSC is greater than 2.3 V, the dynamic range is exceeded and Ratio_{VPC_VSC} is increased; in this condition the DRV on time is more than expected. To ensure the VSC voltage is within range confirm with Equation 4 and Equation 5.

Equation 4.

Equation 5.

where

• V_OUT(min) is the minimum converter output operating voltage of the SR controller.
• V_OUT(max) is the maximum converter output operating voltage of the voltage at OVP.

Discrimination of ringing during DCM operation from valid primary on-time is achieved by a dynamic VPC rising threshold and programmable blanking time. The dynamic threshold V_VPC-TH is 85% typical ratio of the previous VPC pin peak voltage. Referring to Figure 14, the VPC pin voltage is sampled after the VPC voltage is greater than V_VPCEN and V_VPC-TH for t > t_VPC-BLK. The function of the dynamic threshold V_VPC-TH is to reject the ringing in DCM operation from the primary conduction pulses. The dynamic threshold has an active range from the minimum V_VPCEN voltage to a maximum of 1 V clamp. The blanking time is programmable from 200 ns to 1 µs in order to accommodate a variety of converter designs.

Refer to Figure 18 for guidance on selecting the blanking time. The blanking time should be selected as long as reasonable and still accommodate the minimum primary on-time at light-load condition and high-line voltage. In the high-line minimum load condition, select a blanking time that meets the following criteria (Equation 6) to accommodate tolerance of the blanking time and the t_VPC-SPL sampling time window.

For rejection of DCM ringing, the blanking time should be longer than the time that the ring is above the V_VPC-TH dynamic threshold, which is 85% of the minimum SR VDS peak voltage. Determine these criteria at low line and maximum load condition. It is recommended that the transformer turns ratio be selected such that the secondary reflected voltage is < 85% of V_IN(min) bulk capacitor voltage at the highest load when DCM operation occurs at the low line input condition.

To determine the resistor value for t_VPC-BLK use Equation 7 to select from a range of 200 ns to 1 µs.

Equation 7.

where

• t_VPC-BLK is the target blanking time.

Additional discrimination for proper SR timing control is provided by the t_OFF function. Refer to Figure 14 and Figure 15 for the timing details. After the DRV turn off, the DRV is inhibited from turning on again until the t_OFF timer expires. This protects against SR false turn on from SR V_DS DCM ringing below ground.

Figure 18. VPC Blanking Time Criteria

7.3.3 CCM Dead Time

Operation of CCM converters during transition from DCM to CCM results in a number of switching cycles where volt-sec balance is not achieved. To accommodate CCM operation the UCC24630 SR controller incorporates CCM dead-time protection to ensure turn off of the SR MOSFET before the next primary MOSFET turn on. The function provides a limit of the total period of the primary on time plus SR on time to the previous cycle minus the dead time, 600 ns typical. This is accomplished by limiting the SR on time of the active cycle, t (N+1), to the previous recorded cycle, t (N), minus t_CCMDT. As can be seen in Figure 19, the CCM dead time limits the DRV on time even though the VSC volt-sec ramp threshold is not satisfied.

Figure 19. CCM Dead-Time Function

CCM cycle fault provides protection if the switching frequency is unstable during abnormal conditions. The CCM cycle fault triggers if the switching period exceeds the previous switching period by K_CCM-FAULT, 150% typical. The CCM cycle fault disables the DRV output for four consecutive cycles. During the four-cycle disable interval if another CCM cycle fault occurs the fault is retriggered for another four cycles, DRV will not be enabled until four consecutive cycles occur that do not generate a CCM cycle fault. Refer to Figure 20 and Figure 21 for CCM cycle fault behavior.

The N+1 cycle with the longer period sets up the next following cycle to have a longer allowable maximum SR on time based on t(N) – t_CCMDT; if CCM operation occurs in this case the maximum allowable SR on time could conflict with the primary turn on if the converter switching period returns to the previous time. The DRV output is disabled to prevent this potential timing conflict with the primary switch.

Figure 20. CCM Cycle-Fault Behavior, CCM Operation

Figure 21. CCM Cycle-Fault Behavior, DCM Operation

7.3.4 Standby Operation

To minimize power consumption at very light load and standby conditions, the UCC24630 disables the SR DRV output and enters a low current operating state. The criteria for operating in standby mode or normal operation are determined by the average frequency detected on the VPC pin. The frequency detection is compatible with burst mode operation or continuous low frequency FM operation. At start up the device is in normal operation to enable DRV to the SR MOSFET. If < 64 cycles occur in t_ENTO,12.8 ms typical, the device disables the DRV output and enters low-current operating mode with bias current of I_STBY. In standby mode the criteria to enter normal operating mode is when > 32 cycles occur within t_EN, 2.56 ms typical. The device enters normal operation as soon as the 32 cycles occur to reduce the response time exiting standby operation. The average frequency of entering standby mode is 5 kHz typical, and the average frequency of exiting standby mode is 12.5 kHz typical. Refer to Figure 22 for an illustration of standby mode timing.

Figure 22. Standby Mode Operation

7.3.5 Pin Fault Protection

The UCC24630 controller includes fault protection in the event of open pin, shorted pin to ground and abnormal out of range operation.

7.4.1 Start-Up

During start-up when VDD is less than V_VDD(on) the device is disabled. When VDD exceeds the V_VDD(on) UVLO threshold the I_DD goes to I_RUN and the device begins the start sequence detailed in Section 8.3.1 .

7.4.2 Normal Operation

When VDD exceeds V_VDD(on), the VPC voltage exceeds V_VPC-EN and V_VPC-TH, and the VSC voltage exceeds V_VSCEN the DRV output is active. If the switching frequency is above the standby criteria of > 5 kHz the device is in normal operation determining the DRV time based on volt-sec control, or CCM dead time control. I_DD will be I_RUN.

1. The device operates in volt-sec control when the primary on-time plus the DRV on-time is less than the previous cycle minus t_CCMDT. This is the mode of operation the majority of the time.
2. The device operates in CCM dead-time control when the primary on-time plus DRV on time would be greater, as determine by the volt-sec control ramps, than the previous cycle minus t_CCMDT. This occurs only in CCM converters, during the transition of DCM into CCM operation

7.4.3 Standby Operation

If the number of VPC pulses is less than n_ENTO, 64, during t_ENTO the device enters standby mode. DRV operation stops and most device functions are shut down. I_DD is I_STBY during standby operation. To exit standby mode the number of VPC pulses must exceed n_EN, 32, during t_EN. I_DD returns to I_RUN and the DRV output starts after 4 VPC cycles.

7.4.4 Conditions to Stop Operation

The following conditions can disable DRV operation, I_DD is I_RUN during these conditions.

1. VPC overvoltage: When V_VPC > V_VPCDIS for >500 ns the DRV output is disabled for the cycle.
2. CCM Fault: If the current cycle period is greater than the previous cycle times K_{CCM_FAULT}, the DRV output is disabled for 4 cycles. The 4-cycle count can be reset, and extended if another CCM fault occurs during the 4-cycle DRV disable counter.