The VDD pin of the UCC24650 is intended to connect directly to the output voltage of a PSR-flyback converter in the range of 5 to 28 V. Because the device monitors VDD to detect a 3% droop to trigger the wake-up function, the converter output voltage should be sufficiently filtered to avoid false trigger from excessive steady-state ripple voltage, relative to the output voltage. The UCC24650 captures its reference voltage at the end of each flyback demagnetization time to avoid the influence of ringing and switching noise. Converter output capacitance should be sufficient to maintain ΔV_OUT between switching cycles to less than the droop detection threshold.

Avoid an excessive rate of rise on VDD to ensure correct device operation. Ensure that the dv/dt <0.1 V/µs on VDD, or the device may not function until power is removed and restored at a slower rate.