Below is an overview of the system states sequence:

The state transition diagram starts from the un-powered condition of UCC25640x. For device variants that has HV startup, as soon as the AC input is plugged in, the internal JFET of the HV pin will be enabled and will start to deliver current from a source connected from the HV pin to the VCC capacitor. Once the VCC pin voltage exceeds its VCC_{StartSwitching} threshold, the system state will change to JFETOFF. For device variants which does not have HV startup feature, there is no JFETon state. Once VCC exceeds its VCC_{StartSwitching} threshold, the system state will change to JFETOFF. When the PFC output voltage reaches a certain level, the LLC is turned on. Before the LLC starts running, the LO pin is kept high to pull the HS node of the LLC bridge low, thus allowing the capacitor between the HB and HS pins to be charged from VCC via the bootstrap diode. UCC25640x will remain in the CHARGE_BOOT state for a certain time to ensure the boot capacitor is fully charged. When the LLC output voltage reaches a certain level, both PFC and LLC controllers get power from the LLC transformer bias winding. When the load drops below a certain level, the LLC operates in burst mode.

Fault conditions encountered by UCC25640x will cause normal operation to stop, or pause for a certain period of time followed by an automatic re-start. This is to ensure that while a persistent fault condition is present, it is not possible for the temperature of UCC25640x controller or the power converter to rise as a result of the repeated re-start attempts.

Figure 7-21 Block Diagram of System State Machine

Table 7-3 summarizes the inputs and outputs of Figure 7-21.

The state machine is shown in Figure 7-22 and the description of the states and state transition conditions are in the tables below.

Figure 7-22 System State Machine Transition

Figure 7-23 and Figure 7-24 show the most commonly used state transition (assuming no faults during start up states so all the states are captured in the timing diagram). Many different ways of state transitions may happen according to the state machine, but are not captured in this section.

In Figure 7-24, a normal start up procedure is shown. The system enters normal operation and then a fault (OCP, OVP, or OTP) happens.

Figure 7-23 Timing Diagram of System State Machine for UCC256403

Figure 7-24 Timing Diagram of System State Machine for UCC256402 and UCC256404