The soft-start programming and burst mode threshold programming are multiplexed on the pin LL/SS. In addition, when ZCS region operation happens, this pin is pulled down to ground through a diode to increase the switching frequency. The pin block diagram is shown in Figure 7-19.

Figure 7-20 shows the timing diagram of the LL/SS pin programming. It includes 5 phases:

• SS pull low phase - LL/SS pin is internally pulled low with a typical 1.2 kΩ resistor to ground.
• SS initial voltage program phase - The internal pull low is released. As shown in Figure 7-19, LL/SS pin is typically connected with a resistor divider from RVCC and a capacitor to ground. When the internal pull low circuit is released, LL/SS pin voltage can be charged up depending on the external resistor and capacitor. This phase ends when charge boot stage is completed and it has a fixed time of t_{SSInitVolPrgm}.
• Soft start phase - An internal constant current source charges the soft start capacitor right after the charge boot stage, and ends when FBreplica becomes lower than the LL/SS pin voltage. During this phase, LL/SS pin voltage is used as the control effort V_comp. The slow ramp up of LL/SS pin helps the LLC operate at a higher switching frequency when the output voltage is not established yet during startup. This can avoid the large inrush current during startup.
• BMT_L settling phase - When soft start phase is completed, LL/SS pin is used for burst mode threshold programming. As described in Section 7.4.3, two burst mode thresholds are used. During this phase, BMT_H is fixed at either 0.6V (1.2 V if BW option 7 is selected). BMT_L is also fixed which is determined by the programmed ratio of BMT_L/BMT_H. The typical duration of this phase is 600 us.
• BMT_L and BMT_H programming/setting phase - LL/SS pin is buffered at 3.5 V during this phase. Depending on the resistors connected to the pin, LL/SS pin could either sink or source current. If LL/SS pin sinks current, the current will be internally mirrored to flow through R_LL, and the voltage on R_FB is the programmed voltage of BMT_H. If LL/SS pin sources current, the programmed voltage of BMT_H is set to minimal. If the programmed voltage of BMT_H is different from the initial voltage, BMT_H ramps to the target value at a refresh frequency of every 200 us. The slow refresh frequency makes sure that BMT_H does not change due to the noise on LL/SS pin. BMT_L follows the change of BMT_H based on the programmed ratio of BMT_L/BMT_H.

The programmability of the SS initial voltage provides a freedom to limit the maximum switching frequency during startup. This helps to prevent hard switching due to excessively high switching frequency. For applications that require very high switching frequency during startup, an option is also provided to disable the SS initial voltage programming through BW pin, as described in Section 7.4.3.2. If this option is selected, LL/SS pin continues pull low with the internal 1.2 kΩ resistor during the SS initial voltage program phase.

Figure 7-19 LL/SS Block Diagram

Figure 7-20 Timing Diagram of LL/SS Pin Programming